Altera Arria 10 Avalon-ST User Manual
Page 109
When a LMI write has a timing conflict with configuration TLP access, the configuration TLP accesses
have higher priority. LMI writes are held and executed when configuration TLP accesses are no longer
pending. An acknowledge signal is sent back to the Application Layer when the execution is complete.
All LMI reads are also held and executed when no configuration TLP requests are pending. The LMI
interface supports two operations: local read and local write. The timing for these operations complies
with the Avalon-MM protocol described in the Avalon Interface Specifications. LMI reads can be issued at
any time to obtain the contents of any Configuration Space register. LMI write operations are not
recommended for use during normal operation. The Configuration Space registers are written by requests
received from the PCI Express link and there may be unintended consequences of conflicting updates
from the link and the LMI interface. LMI Write operations are provided for AER header logging, and
debugging purposes only.
• In Root Port mode, do not access the Configuration Space using TLPs and the LMI bus simultane‐
ously.
Table 6-13: LMI Interface
Signal
Direction
Description
lmi_dout[7:0]
Output Data outputs. Data is driven from LSB, [7:0], to MSB,[31:24]. The
LSB coincides with
lmi_ack
.
lmi_rden
Input
Read enable input.
lmi_wren
Input
Write enable input.
lmi_ack
Output Write execution done/read data valid.
lmi_addr[11:0]
Input
Address inputs, [1:0] not used.
lmi_din[7:0]
Input
Data inputs. Data is driven from LSB, [7:0], to MSB,[31:24]. The LSB
coincides with
lim_wren
.
Figure 6-35: LMI Read
clk
read_en
addr_in[11:0]
dataout[7:0]
rd_wr_ack
bits[7:0]
bits[15:8]
bits[23:16]
bits[31:24]
UG-01145_avst
2015.05.04
LMI Signals
6-43
Interfaces and Signal Descriptions
Altera Corporation