Altera Arria 10 Avalon-ST - Manual (Page 6)

Chaining DMA Control and Status Registers ...........................................................................17-9
Chaining DMA Descriptor Tables ........................................................................................... 17-12
Test Driver Module ................................................................................................................................ 17-15
DMA Write Cycles ................................................................................................................................. 17-16
DMA Read Cycles ...................................................................................................................................17-18
Root Port Design Example .................................................................................................................... 17-20
Root Port BFM ........................................................................................................................................ 17-22
BFM Memory Map .....................................................................................................................17-24
Configuration Space Bus and Device Numbering ................................................................. 17-24
Configuration of Root Port and Endpoint ..............................................................................17-24
Issuing Read and Write Transactions to the Application Layer .......................................... 17-29
BFM Procedures and Functions ........................................................................................................... 17-30
ebfm_barwr Procedure .............................................................................................................. 17-30
ebfm_barwr_imm Procedure ....................................................................................................17-31
ebfm_barrd_wait Procedure ..................................................................................................... 17-32
ebfm_barrd_nowt Procedure ....................................................................................................17-33
ebfm_cfgwr_imm_wait Procedure ...........................................................................................17-34
ebfm_cfgwr_imm_nowt Procedure ......................................................................................... 17-34
ebfm_cfgrd_wait Procedure ......................................................................................................17-35
ebfm_cfgrd_nowt Procedure .....................................................................................................17-36
BFM Configuration Procedures................................................................................................ 17-37
BFM Shared Memory Access Procedures ............................................................................... 17-39
BFM Log and Message Procedures .......................................................................................... 17-42
Verilog HDL Formatting Functions ........................................................................................ 17-46
Procedures and Functions Specific to the Chaining DMA Design Example...................... 17-50
Setting Up Simulation.............................................................................................................................17-57
Changing Between Serial and PIPE Simulation ..................................................................... 17-57
Using the PIPE Interface for Gen1 and Gen2 Variants .........................................................17-57
Viewing the Important PIPE Interface Signals........................................................................17-57
Disabling the Scrambler for Gen1 and Gen2 Simulations .................................................... 17-57
Disabling 8B/10B Encoding and Decoding for Gen1 and Gen2 Simulations.....................17-58
Debugging .........................................................................................................18-1
Simulation Fails To Progress Beyond Polling.Active State..................................................................18-1
Hardware Bring-Up Issues ...................................................................................................................... 18-1
Link Training .............................................................................................................................................18-2
Debugging Link Failure in L0 Due To Deassertion of tx_st_ready ....................................... 18-2
Use Third-Party PCIe Analyzer ..............................................................................................................18-5
BIOS Enumeration Issues ........................................................................................................................18-5
Frequently Asked Questions.............................................................................. A-1
Lane Initialization and Reversal ........................................................................B-1
Additional Information......................................................................................C-1
TOC-6 Getting Started with the Arria 10 Hard IP for PCI Express with the Avalon-ST Interface
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