Altera Arria 10 Avalon-ST User Manual
Page 270
Date
Version
Changes Made
• Removed
txdatavalid0
signal from the PIPE interface. This
signal is not available.
• Removed references to the MegaWizard
®
Plug-In Manager. In
14.0 the IP Parameter Editor Powered by Qsys has replaced the
MegaWizard Plug-In Manager.
• Made the following changes to the timing diagram, Hard IP
Reconfiguration Bus Timing of Read-Only Registers:
• Added
hip_reconfig_rst_n
.
• Changed timing of
avmm_rdata[15:0]
. Valid data returns 4
cycles after
avmm_rd
.
• Added link to a Knowledge Base Solution that shows how to
observe the
test_in
bus for debugging.
• Removed optional 125 MHz reference clock frequency. This
option has not been tested extensively in hardware.
• Corrected channel placement diagrams for Gen3 x2 and Gen3 x4.
The CMU PLL should be shown in the Channel 4 location. For
Gen3 x2, the second data channel is Ch1. For Gen3 x4, the data
channels are Ch0 - Ch3.
• Corrected figure showing physical placement of PCIe Hard IP
modules for Arria V GZ devices.
• Added definition for
test_in[6]
and link to Knowledge Base
Solution on observing the PIPE interface signals on the
test_out
bus.
• Removed references to Gen2 x1 62.5 MHz configuration. This
configuration is not supported.
• Removed statement that Gen1 and Gen2 designs do not require
transceiver reconfiguration. Gen1 and Gen2 designs may require
transceiver reconfiguration to improve signal quality.
• Removed
reconfig_busy
port from connect between PHY IP
Core for PCI Express and the Transceiver Reconfiguration
Controller in the Altera Transceiver Reconfiguration Controller
Connectivity figure. The Transceiver Reconfiguration Controller
drives
reconfig_busy
port to the Altera PCIe Reconfig Driver.
• Removed soft reset controller
.sdc
constraints from the
/ip/altera/altera_pcie/altera_pcie_hip_ast_ed/altpcied_
example. These constraints are now in a separate file in the
synthesis/submodules
directory.
• Updated Power Supply Voltage Requirements table.
• For Arria 10 devices, updated Physical Placement of the Arria 10
Hard IP for PCIe IP and Channels to show GT devices instead of
GX devices.
• For Arria 10 devices, corrected frequency of
hip_reconfig_lck
. I
should be 125 MHz.
C-4
Revision History for the Avalon-ST Interface
UG-01145_avst
2015.05.04
Altera Corporation
Additional Information