Arria 10 reset and clocks, Arria 10 reset and clocks -1, Figure 8-1: reset controller in arria 10 devices – Altera Arria 10 Avalon-ST User Manual
Page 144
Arria 10 Reset and Clocks
8
2015.05.04
UG-01145_avst
Figure 8-1: Reset Controller in Arria 10 Devices
Example Design
_
altpcied_
Transceiver Hard
Reset Logic/Soft Reset
Controller
Configuration Space
Sticky Registers
Datapath State
Machines of
Hard IP Core
SERDES
Configuration Space
Non-Sticky Registers
reset_status
pld_clk
pin_perst
npor
refclk
srst
crst
pld_clk_inuse
Hard IP for PCI Express
altpcie_
altpcie_rs_serdes.v
coreclkout_hip
top.v
tx_digitalrst
rx_analogrst
rx_digitalrst
APPs
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