Altera Arria 10 Avalon-ST - Manual (Page 52)

Device Capabilities
Table 4-6: Capabilities Registers
Parameter Possible Values Default Value Description
Maximum
payload size
128 bytes
256 bytes
512 bytes
1024 bytes
2048 bytes
128 bytes Specifies the maximum payload size supported. This
parameter sets the read-only value of the max payload
size supported field of the Device Capabilities register
(0x084[2:0]). Address: 0x084.
Number of
Tags
supported
32
64 32 Indicates the number of tags supported for non-posted
requests transmitted by the Application Layer. This
parameter sets the values in the Device Control register
(0x088) of the PCI Express capability structure
described in Table 9–9 on page 9–5.
The Transaction Layer tracks all outstanding
completions for non-posted requests made by the
Application Layer. This parameter configures the
Transaction Layer for the maximum number of Tags
supported to track. The Application Layer must set the
tag values in all non-posted PCI Express headers to be
less than this value. Values greater than 32 also set the
extended tag field supported bit in the Configuration
Space Device Capabilities register. The Application
Layer can only use tag numbers greater than 31 if
configuration software sets the Extended Tag Field
Enable bit of the Device Control register. This bit is
available to the Application Layer on the
tl_cfg_ctl
output signal as
cfg_devcsr[8]
.
Completion
timeout
range
ABCD
BCD
ABC
AB
B
A
None
ABCD Indicates device function support for the optional
completion timeout programmability mechanism. This
mechanism allows system software to modify the
completion timeout value. This field is applicable only to
Root Ports and Endpoints that issue requests on their
own behalf. Completion timeouts are specified and
enabled in the Device Control 2 register (0x0A8) of the
PCI Express Capability Structure Version. For all other
UG-01145_avst
2014.08.18
Device Capabilities 4-9
Parameter Settings Altera Corporation
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