Altera Arria 10 Avalon-ST Instruction Manuals and User Guides
We have 1 Instruction Manual and User Guide for Arria 10 Avalon-ST Altera
Manuals 
| Recognized languages: | English |
|---|---|
| Pages: | 275 |
| Size: | 2.29 MB |
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Document Outline
- Arria 10 Avalon-ST Interface for PCIe Solutions User Guide
- Contents
- 1. Datasheet
- 2. Getting Started with the Arria 10 Hard IP for PCI Express
- Qsys Design Flow
- Generating the Testbench
- Simulating the Example Design
- Generating Quartus II Synthesis Files
- Understanding the Files Generated
- Understanding Simulation Log File Generation
- Understanding Physical Placement of the PCIe IP Core
- Adding Virtual Pin Assignment to the Quartus II Settings File (.qsf)
- Compiling the Design in the Qsys Design Flow
- Modifying the Example Design
- Using the IP Catalog To Generate Your Arria 10 Hard IP for PCI Express as a Separate Component
- Files Generated for Altera IP Cores
- Qsys Design Flow
- 3. Getting Started with the Configuration Space Bypass Mode Qsys Example Design
- 4. Parameter Settings
- 5. Physical Layout of Hard IP In Arria 10 Devices
- 6. Interfaces and Signal Descriptions
- Avalon‑ST RX Interface
- Avalon-ST TX Interface
- Clock Signals
- Reset, Status, and Link Training Signals
- ECRC Forwarding
- Error Signals
- Interrupts for Endpoints
- Interrupts for Root Ports
- Completion Side Band Signals
- Parity Signals
- LMI Signals
- Transaction Layer Configuration Space Signals
- Hard IP Reconfiguration Interface
- Power Management Signals
- Physical Layer Interface Signals
- 7. Registers
- Correspondence between Configuration Space Registers and the PCIe Specification
- Type 0 Configuration Space Registers
- PCI Express Capability Structures
- Altera-Defined VSEC Registers
- CvP Registers
- Uncorrectable Internal Error Mask Register
- Uncorrectable Internal Error Status Register
- Correctable Internal Error Mask Register
- Correctable Internal Error Status Register
- 8. Arria 10 Reset and Clocks
- 9. Interrupts
- 10. Error Handling
- 11. IP Core Architecture
- 12. Transaction Layer Protocol (TLP) Details
- 13. Throughput Optimization
- 14. Design Implementation
- 15. Optional Features
- 16. Hard IP Reconfiguration
- 17. Testbench and Design Example
- Endpoint Testbench
- Root Port Testbench
- Chaining DMA Design Examples
- Test Driver Module
- DMA Write Cycles
- DMA Read Cycles
- Root Port Design Example
- Root Port BFM
- BFM Procedures and Functions
- ebfm_barwr Procedure
- ebfm_barwr_imm Procedure
- ebfm_barrd_wait Procedure
- ebfm_barrd_nowt Procedure
- ebfm_cfgwr_imm_wait Procedure
- ebfm_cfgwr_imm_nowt Procedure
- ebfm_cfgrd_wait Procedure
- ebfm_cfgrd_nowt Procedure
- BFM Configuration Procedures
- BFM Shared Memory Access Procedures
- BFM Log and Message Procedures
- Verilog HDL Formatting Functions
- Procedures and Functions Specific to the Chaining DMA Design Example
- Setting Up Simulation
- 18. Debugging
- A. Frequently Asked Questions
- B. Lane Initialization and Reversal
- C. Additional Information