Altera Arria 10 Avalon-ST - Manual (Page 26)

Files Generated for Altera IP Cores
Figure 2-3: IP Core Generated Files
_tb.csv
_tb.spd
.cmp - VHDL component declaration file
.ppf - XML I/O pin information file
.qip - Lists IP synthesis files
.sip - Contains assingments for IP simulation files
.v or .vhd
Top-level IP synthesis file .v or .vhd
Top-level simulation file
.qsys - System or IP integration file
_bb.v - Verilog HDL black box EDA synthesis file
_inst.v or .vhd - Sample instantiation template
_generation.rpt - IP generation report
.debuginfo - Contains post-generation information
.html - Connection and memory map data
.bsf - Block symbol schematic
.spd - Combines simulation scripts for multiple cores
_tb.qsys
Testbench system file
.sopcinfo - Software tool-chain integration file
scripts>
IP variation files
_tb
testbench system
sim
Simulation files
synth
IP synthesis files
sim
simulation files
Simulator scripts
_tb
n
Subcore libraries
sim
Subcore
Simulation files
synth
Subcore
synthesis files
n
IP variation files
testbench files
Related Information
• Making Pin Assignments to Assign I/O Standard to Serial Data Pins on page 14-1
• Test Signals on page 6-62
• Reset, Status, and Link Training Signals on page 6-31
• Generating the Testbench on page 2-3
• Simulating the Example Design on page 3-5
• Simulating the Example Design on page 3-5
Modifying the Example Design
To use this example design as the basis of your own design, replace the Chaining DMA Example shown in
the following figure with your own Application Layer design. Then modify the Root Port BFM driver to
generate the transactions needed to test your Application Layer.
UG-01145_avst
2015.05.04
Modifying the Example Design 2-7
Getting Started with the Arria 10 Hard IP for PCI Express Altera Corporation
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