For more information refer to, Tradeoffs to consider when, Enabling multiple packets per cycle – Altera Arria 10 Avalon-ST User Manual

Page 81

Data Alignment and Timing for 256‑Bit Avalon‑ST RX Interface

Figure 6-16: Location of Headers and Data for Avalon-ST 256-Bit Interface

The following figure shows the location of headers and data for the 256-bit Avalon-ST packets. This

layout of data applies to both the TX and RX buses.

255

4DW header,

Aligned data

4DW header,

Unaligned data

3DW header,

Aligned data

3DW header,

Unaligned data

Figure 6-17: 256-Bit Avalon-ST RX Packets Use of rx_st_empty and Single-Cycle Packets

The following figure illustrates two single-cycle 256-bit packets. The first packet has two empty qword,

rx_st_data[191:0]

is valid. The second packet has two empty dwords;

rx_st_data[127:0]

is valid.

pld_clk

rx_st_data[255:0]

rx_st_sop

rx_st_eop

rx_st_empty[1:0]

rx_st_ready

rx_st_valid

XX..BE ...

XXXXXXXXXXXXXXXX. . . 4592001487DF08876210...

Tradeoffs to Consider when Enabling Multiple Packets per Cycle

If you enable Multiple Packets Per Cycle under the Systems Settings heading, a TLP can start on a

128-bit boundary. This mode supports multiple start of packet and end of packet signals in a single cycle

when the Avalon-ST interface is 256 bits wide. It reduces the wasted bandwidth for small packets.
A comparison of the largest and smallest packet sizes illustrates this point. Large packets using the full

256 bits achieve the following throughput:

256/256*8 = 8 GBytes/sec

UG-01145_avst

2015.05.04

Data Alignment and Timing for 256‑Bit Avalon‑ST RX Interface

6-15

Interfaces and Signal Descriptions

Altera Corporation

Send Feedback