Altera Arria 10 Avalon-ST User Manual

Page 36

1. To observe the simulation, on the ModelSim View menu, select wave. Then add some key interfaces to

the wave window. The following four interfaces under the

/top_tb/top_inst/apps/altpcierd_cfbp_top/

cfgbp_app_ctrl/genblk1

illustrate the TX and RX interfaces, the current state, and configuration.

• *RxSt*

• *TxSt*

• *Rxm*

• *_state*

• cfg_*

2. To run the simulation, type the following command:

run -all

Note: By default, the simulation is serial, to simulate using the parallel PIPE interface, you can change the

default value of the

serial_sim_hwtcl

parameter from 1 to 0 in

altera_pcie_cfgbp_ed/top/testbench/

top_tb/simulation/top_tb.v

. After changing that value, you must recompile the simulation to pick up

the new value of the

serial_sim_hwtcl

parameter before running the simulation.

Timing for Configuration Read to Function 0 for the 256-Bit Avalon-ST Interface

The following timing diagram illustrates a Configuration Read to Function 0 starting at time 60568 ns in

the simulation.

3-6

Timing for Configuration Read to Function 0 for the 256-Bit Avalon-ST Interface

UG-01145_avst

2014.08.18

Altera Corporation

Getting Started with the Configuration Space Bypass Mode Qsys Example Design