Test driver module, Test driver module -15 – Altera Arria 10 Avalon-ST User Manual
Page 215
Descriptor Field
Endpoint
Access
RC Access
Description
RC Address
Upper DWORD
R
R/W
Specifies the upper base address of the memory
transfer on the RC site.
RC Address
Lower DWORD
R
R/W
Specifies the lower base address of the memory
transfer on the RC site.
DMA Length
R
R/W
Specifies the number of DMA DWORDs to transfer.
EPLAST_ENA
R
R/W
This bit is
OR
’d with the
EPLAST_ENA
bit of the control
register. When
EPLAST_ENA
is set, the Endpoint DMA
module updates the EPLAST field of the descriptor
table with the number of the last completed
descriptor, in the form <0 – n>. Refer to
on page 17-12 for more
information.
MSI_ENA
R
R/W
This bit is
OR
’d with the
MSI
bit of the descriptor
header. When this bit is set the Endpoint DMA
module sends an interrupt when the descriptor is
completed.
Test Driver Module
The BFM driver module, altpcietb_bfm_driver_chaining.v is configured to test the chaining DMA
example Endpoint design. The BFM driver module configures the Endpoint Configuration Space registers
and then tests the example Endpoint chaining DMA channel. This file is stored in the
testbench/
directory.
The BFM test driver module performs the following steps in sequence:
1. Configures the Root Port and Endpoint Configuration Spaces, which the BFM test driver module does
by calling the procedure
ebfm_cfg_rp_ep
, which is part of altpcietb_bfm_configure.
2. Finds a suitable BAR to access the example Endpoint design Control Register space. Either BARs 2 or 3
must be at least a 256-byte memory BAR to perform the DMA channel test. The
find_mem_bar
procedure in the altpcietb_bfm_driver_chaining does this.
3. If a suitable BAR is found in the previous step, the driver performs the following tasks:
a. DMA read—The driver programs the chaining DMA to read data from the BFM shared memory
into the Endpoint memory. The descriptor control fields are specified so that the chaining DMA
completes the following steps to indicate transfer completion:
• The chaining DMA writes the
EPLast
bit of the Chaining DMA Descriptor Table after finishing
the data transfer for the first and last descriptors.
• The chaining DMA issues an MSI when the last descriptor has completed.
UG-01145_avst
2015.05.04
Test Driver Module
17-15
Testbench and Design Example
Altera Corporation