Altera Arria 10 Avalon-ST - Manual (Page 148)

As this figure indicates, the IP core includes the following clock domains:
coreclkout_hip
Table 8-1: Application Layer Clock Frequency for All Combinations of Link Width, Data Rate and
Application Layer Interface Widths
The
coreclkout_hip
signal is derived from
pclk
. The following table lists frequencies for
coreclkout_hip
,
which are a function of the link width, data rate, and the width of the Application Layer to Transaction Layer
interface. The frequencies and widths specified in this table are maintained throughout operation. If the link
downtrains to a lesser link width or changes to a different maximum link rate, it maintains the frequencies it was
originally configured for as specified in this table. (The Hard IP throttles the interface to achieve a lower
throughput.)
Link Width Maximum Link Rate Avalon Interface Width coreclkout_hip
×1 Gen1
64 62.5 MHz (4)
×1 Gen1
64
125 MHz
×2 Gen1
64
125 MHz
×4 Gen1
64
125 MHz
×8 Gen1 64 250 MHz
×8 Gen1
128
125 MHz
×1
Gen2 64
125 MHz
×2
Gen2 64
125 MHz
×4 Gen2 64 250 MHz
×4 Gen2 128 125 MHz
×8 Gen2 128 250 MHz
×8 Gen2 256 125 MHz
×1
Gen3 64
125 MHz
×2
Gen3 64
125 MHz
×2
Gen3 128
250 MHz
×4 Gen3 128 250 MHz
(4) This mode saves power
UG-01145_avst
2015.05.04
coreclkout_hip 8-5
Arria 10 Reset and Clocks Altera Corporation
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