Altera Arria 10 Avalon-ST User Manual
Page 90
Figure 6-21: 64-Bit Avalon-ST tx_st_data Cycle Definition for TLP 4-Dword Header with Non-Qword
Aligned Address
pld_clk
tx_st_data[63:32]
tx_st_data[31:0]
tx_st_sop
tx_st_eop
Header 1
Header3
Data0
Data2
Header 0
Header2
Data1
Figure 6-22: 64-Bit Transaction Layer Backpressures the Application Layer
The following figure illustrates the timing of the TX interface when the Arria 10 Hard IP for PCI Express
pauses transmission by the Application Layer by deasserting
tx_st_ready
. Because the
readyLatency
is
two cycles, the Application Layer deasserts
tx_st_valid
after two cycles and holds
tx_st_data
until two
cycles after
tx_st_ready
is asserted.
coreclkout
tx_st_sop
tx_st_eop
tx_st_ready
tx_st_valid
tx_st_err
tx_st_data[63:0]
.
.
.
.
.
.
.
.
.
.
readyLatency
00. . 00 ...
BB...
BB ...
BBBB0306BBB0305
BB...
BB..
BB ...
BB ...
BB ... BB ...
BB... .
6-24
Data Alignment and Timing for the 64‑Bit Avalon-ST TX Interface
UG-01145_avst
2015.05.04
Altera Corporation
Interfaces and Signal Descriptions
- MAX 10 JTAG (15 pages)
- MAX 10 Power (21 pages)
- Unique Chip ID (12 pages)
- Remote Update IP Core (43 pages)
- Device-Specific Power Delivery Network (28 pages)
- Device-Specific Power Delivery Network (32 pages)
- Hybrid Memory Cube Controller (69 pages)
- ALTDQ_DQS IP (117 pages)
- MAX 10 Embedded Memory (71 pages)
- MAX 10 Embedded Multipliers (37 pages)
- MAX 10 Clocking and PLL (86 pages)
- MAX 10 FPGA (26 pages)
- MAX 10 FPGA (56 pages)
- USB-Blaster II (22 pages)
- GPIO (22 pages)
- LVDS SERDES (27 pages)
- User Flash Memory (33 pages)
- ALTDQ_DQS2 (100 pages)
- Avalon Tri-State Conduit Components (18 pages)
- Cyclone V Avalon-MM (166 pages)
- Cyclone III FPGA Starter Kit (36 pages)
- Cyclone V Avalon-ST (248 pages)
- Stratix V Avalon-ST (286 pages)
- Stratix V Avalon-ST (293 pages)
- DDR3 SDRAM High-Performance Controller and ALTMEMPHY IP (10 pages)
- Avalon Verification IP Suite (224 pages)
- Avalon Verification IP Suite (178 pages)
- FFT MegaCore Function (50 pages)
- DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP (140 pages)
- Floating-Point (157 pages)
- Integer Arithmetic IP (157 pages)
- Embedded Peripherals IP (336 pages)
- JESD204B IP (158 pages)
- Low Latency Ethernet 10G MAC (109 pages)
- LVDS SERDES Transmitter / Receiver (72 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (3 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (80 pages)
- IP Compiler for PCI Express (372 pages)
- Parallel Flash Loader IP (57 pages)
- Nios II C2H Compiler (138 pages)
- RAM-Based Shift Register (26 pages)
- RAM Initializer (36 pages)
- Phase-Locked Loop Reconfiguration IP Core (51 pages)
- DCFIFO (28 pages)