Avalon‑st rx interface, Avalon-st rx interface -2 – Altera Arria 10 Avalon-ST User Manual
Page 68

Avalon‑ST RX Interface
The following table describes the signals that comprise the Avalon-ST RX Datapath. The RX data signal
can be 64, 128, or 256 bits.
Table 6-1: 64-, 128-, or 256‑Bit Avalon-ST RX Datapath
Signal
Direction
Description
rx_st_data[
Output
Receive data bus. Refer to figures following this table for the
mapping of the Transaction Layer’s TLP information to
rx_st_
data
and examples of the timing of this interface. Note that the
position of the first payload dword depends on whether the TLP
address is qword aligned. The mapping of message TLPs is the
same as the mapping of TLPs with 4-dword headers. When using
a 64-bit Avalon-ST bus, the width of
rx_st_data
is 64. When
using a 128-bit Avalon-ST bus, the width of
rx_st_data
is 128.
When using a 256-bit Avalon-ST bus, the width of
rx_st_data
is
256 bits.
rx_st_sop[1:0]
Output
Indicates that this is the first cycle of the TLP when
rx_st_valid
is asserted. When using a 256-bit Avalon-ST bus the following
correspondences apply:
When you turn on Enable multiple packets per cycle,
• bit 0 indicates that a TLP begins in
rx_st_data[127:0]
• bit 1 indicates that a TLP begins in
rx_st_data[255:128]
In single packet per cycle mode, this signal is a single bit which
indicates that a TLP begins in this cycle.
rx_st_eop[1:0]
Output
Indicates that this is the last cycle of the TLP when
rx_st_valid
is asserted.
When using a 256-bit Avalon-ST bus the following correspond‐
ences apply:
When you turn on Enable multiple packets per cycle,
• bit 0 indicates that a TLP ends in
rx_st_data[127:0]
• bit 1 indicates that a TLP ends in
rx_st_data[255:128]
In single packet per cycle mode, this signal is a single bit which
indicates that a TLP ends in this cycle.
rx_st_empty[1:0]
Output
Indicates the number of empty qwords in
rx_st_data
. Not used
when
rx_st_data
is 64 bits. Valid only when
rx_st_eop
is
asserted in 128-bit and 256-bit modes.
6-2
Avalon‑ST RX Interface
UG-01145_avst
2015.05.04
Altera Corporation
Interfaces and Signal Descriptions