Altera Arria 10 Avalon-ST - Manual (Page 48)

Parameter Value Description
Enable Altera
Debug Master
Endpoint
(ADME)
On/Off
When On, you can use the Altera System Console to read and write
the embedded Arria 10 Native PHY registers.
Table 4-2: Interface System Settings
Parameter Value Description
Application
Interface
64-bit
128-bit
256-bit
Specifies the data width for the Application Layer to Transac‐
tion Layer interface.
Refer to Application Layer Clock Frequency for All Combina‐
tions of Link Width, Data Rate and Application Layer Interface
Widths for all legal combinations of data width, number of
lanes, Application Layer clock frequency, and data rate.
Related Information
• Throughput Optimization on page 13-1
• Configuration via Protocol (CvP) on page 15-1
• PCI Express Base Specification 3.0
• Arria 10 Transceiver PHY User Guide
Provides information about the ADME feature for Arria 10 devices.
Base Address Register (BAR) and Expansion ROM Settings
The type and size of BARs available depend on port type.
UG-01145_avst
2014.08.18
Base Address Register (BAR) and Expansion ROM Settings 4-5
Parameter Settings Altera Corporation
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