Altera Arria 10 Avalon-ST User Manual

Page 76

Figure 6-7: 64-Bit Application Layer Backpressures Transaction Layer

The following figure illustrates the timing of the RX interface when the Application Layer backpressures

the Arria 10 Hard IP for PCI Express by deasserting

_st_ready

. The

rx_st_valid

signal deasserts

within three cycles after

rx_st_ready

is deasserted. In this example,

rx_st_valid

is deasserted in the

next cycle.

rx_st_data

is held until the Application Layer is able to accept it.

pld_clk

rx_st_data[63:0]

rx_st_sop

rx_st_eop

rx_st_ready

rx_st_valid

000 . 010 .

CCCC0002CCCC0001

. CC

Figure 6-8: 4-Bit Avalon-ST Interface Back-to-Back Transmission

The following figure illustrates back-to-back transmission on the 64-bit Avalon-ST RX interface with no

idle cycles between the assertion of

rx_st_eop

and

rx_st_sop

pld_clk

rx_st_data[63:0]

rx_st_sop

rx_st_eop

rx_st_ready

rx_st_valid

C. C. C. C. CCCC0089002...

C. C. C. C. C. C. C. C. C. C. C. C. C. C. C. C. C. C. C. C. C. C. C. C. C. C. C C

Related Information

Avalon Interface Specifications

6-10

Data Alignment and Timing for the 64‑Bit Avalon‑ST RX Interface

UG-01145_avst

2015.05.04

Altera Corporation

Interfaces and Signal Descriptions

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