Altera Arria 10 Avalon-ST - Manual (Page 27)

Figure 2-4: Testbench for PCI Express
Hard IP for PCI Express
Altera FPGA
PCB
Root
Port
BFM
perstn (npor)
Reset
APPS DUT
Chaining DMA
(User Application) Transaction Layer
Data Link Layer
PHY MAC Layer
PHY IP Core for PCI Express
Using the IP Catalog To Generate Your Arria 10 Hard IP for PCI Express as a Separate
Component
You can also instantiate the Arria 10 Hard IP for PCI Express IP Core as a separate component for
integration into your project.
You can use the Quartus II IP Catalog and IP Parameter Editor to select, customize, and generate files
representing your custom IP variation. The IP Catalog (Tools > IP Catalog) automatically displays IP
cores available for your target device. Double-click any IP core name to launch the parameter editor and
generate files representing your IP variation.
For more information about the customizing and generating IP Cores refer to Specifying IP Core
Parameters and Options in Introduction to Altera IP Cores. For more information about upgrading older
IP cores to the current release, refer to Upgrading Outdated IP Cores in Introduction to Altera IP Cores.
Related Information
• Qsys Design Flow on page 2-2
• Introduction to Altera IP Cores
• Managing Quartus II Projects
2-8 Using the IP Catalog To Generate Your Arria 10 Hard IP for PCI Express as a Separate
Component
UG-01145_avst
2015.05.04
Altera Corporation Getting Started with the Arria 10 Hard IP for PCI Express
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