Altera Arria 10 Avalon-ST User Manual
Page 213
tors. The Endpoint chaining DMA application accesses the Chaining DMA descriptor table for two
reasons:
• To iteratively retrieve four-dword descriptors to start a DMA
• To send update status to the RP, for example to record the number of descriptors completed to the
descriptor header
Each subsequent descriptor consists of a minimum of four dwords of data and corresponds to one DMA
transfer. (A dword equals 32 bits.)
Note: The chaining DMA descriptor table should not cross a 4 KByte boundary.
Table 17-7: Chaining DMA Descriptor Table
Byte Address
Offset to Base
Source
Descriptor Type
Description
0x0
Descriptor Header
Reserved
0x4
Reserved
0x8
Reserved
0xC
EPLAST - when enabled by the
EPLAST_ENA
bit in the
control register or descriptor, this location records the
number of the last descriptor completed by the chaining
DMA module.
0x10
Descriptor 0
Control fields, DMA length
0x14
Endpoint address
0x18
RC address upper dword
0x1C
RC address lower dword
0x20
Descriptor 1
Control fields, DMA length
0x24
Endpoint address
0x28
RC address upper dword
0x2C
RC address lower dword
. . .
UG-01145_avst
2015.05.04
Chaining DMA Descriptor Tables
17-13
Testbench and Design Example
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