Altera Arria 10 Avalon-ST User Manual
Page 228
Figure 17-6: Memory Space Layout—No Limit
Root Complex
Shared Memory
Unused
Unused
Configuration Scratch
Space Used by
Routines - Not
Writeable by User
Calls or Endpoint
BAR Table
Used by BFM
Routines - Not
Writeable by User
Calls or Endpoint
Endpoint Non-
Prefetchable Memory
Space BARs
Assigned Smallest
to Largest
Endpoint Memory
Space BARs
Prefetchable 64-bit
Assigned Smallest
to Largest
Endpoint Memory
Space BARs
Prefetchable 32-bit
Assigned Smallest
to Largest
BAR-Size Dependent
BAR-Size Dependent
BAR-Size Dependent
0x0000 0001 0000 0000
0xFFFF FFFF FFFF FFFF
0x0020 0000
0x0000 0000
Address
0x001F FF00
0x001F FF80
The following figure shows the I/O address space.
17-28
Configuration of Root Port and Endpoint
UG-01145_avst
2015.05.04
Altera Corporation
Testbench and Design Example
- MAX 10 JTAG (15 pages)
- MAX 10 Power (21 pages)
- Unique Chip ID (12 pages)
- Remote Update IP Core (43 pages)
- Device-Specific Power Delivery Network (28 pages)
- Device-Specific Power Delivery Network (32 pages)
- Hybrid Memory Cube Controller (69 pages)
- ALTDQ_DQS IP (117 pages)
- MAX 10 Embedded Memory (71 pages)
- MAX 10 Embedded Multipliers (37 pages)
- MAX 10 Clocking and PLL (86 pages)
- MAX 10 FPGA (26 pages)
- MAX 10 FPGA (56 pages)
- USB-Blaster II (22 pages)
- GPIO (22 pages)
- LVDS SERDES (27 pages)
- User Flash Memory (33 pages)
- ALTDQ_DQS2 (100 pages)
- Avalon Tri-State Conduit Components (18 pages)
- Cyclone V Avalon-MM (166 pages)
- Cyclone III FPGA Starter Kit (36 pages)
- Cyclone V Avalon-ST (248 pages)
- Stratix V Avalon-ST (286 pages)
- Stratix V Avalon-ST (293 pages)
- DDR3 SDRAM High-Performance Controller and ALTMEMPHY IP (10 pages)
- Avalon Verification IP Suite (224 pages)
- Avalon Verification IP Suite (178 pages)
- FFT MegaCore Function (50 pages)
- DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP (140 pages)
- Floating-Point (157 pages)
- Integer Arithmetic IP (157 pages)
- Embedded Peripherals IP (336 pages)
- JESD204B IP (158 pages)
- Low Latency Ethernet 10G MAC (109 pages)
- LVDS SERDES Transmitter / Receiver (72 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (3 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (80 pages)
- IP Compiler for PCI Express (372 pages)
- Parallel Flash Loader IP (57 pages)
- Nios II C2H Compiler (138 pages)
- RAM-Based Shift Register (26 pages)
- RAM Initializer (36 pages)
- Phase-Locked Loop Reconfiguration IP Core (51 pages)
- DCFIFO (28 pages)