Altera Arria 10 Avalon-ST - Manual (Page 221)

Figure 17-3: Root Port Design Example
Root Port
Variation
(variation_name.v)
Avalon-ST Interface
(altpcietb_bfm_vc_intf)
Test Driver
(altpcietb_bfm_
driver_rp.v)
BFM Shared Memory
(altpcietb_bfm_shmem
_common)
BFM Read/Write Shared Request Procedures
BFM Configuration Procedures
BFM Request Interface
(altpcietb_bfm_req_intf_common)
BFM Log Interface
(altpcietb_bfm_log
_common)
PCI Express
Link
Root Port BFM Tasks and Shared Memory
altpcietb_bfm_ep_example_chaining_pipe1b.v
Avalon-ST
You can use the example Root Port design for Verilog HDL simulation. All of the modules necessary to
implement the example design with the variation file are contained in
altpcietb_bfm_ep_example_chaining_pipen1b.v.
UG-01145_avst
2015.05.04
Root Port Design Example 17-21
Testbench and Design Example Altera Corporation
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