Altera Arria 10 Avalon-ST User Manual
Page 151
Figure 9-1: MSI Handler Block
MSI Handler
Block
app_msi_req
app_msi_ack
app_msi_tc[2:0]
app_msi_num[4:0]
pex_msi_num
app_int_sts
cfg_msicsr[15:0]
The following figure illustrates a possible implementation of the MSI handler block with a per vector
enable bit. A global Application Layer interrupt enable can also be implemented instead of this per vector
MSI.
Figure 9-2: Example Implementation of the MSI Handler Block
app_int_en0
app_int_sts0
app_msi_req0
app_int_en1
app_int_sts1
app_msi_req1
app_int_sts
MSI
Arbitration
msi_enable & Master Enable
app_msi_req
app_msi_ack
Vector 1
Vector 0
IRQ
Generation
App Layer
IRQ
Generation
App Layer
R/W
R/W
There are 32 possible MSI messages. The number of messages requested by a particular component does
not necessarily correspond to the number of messages allocated. For example, in the following figure, the
Endpoint requests eight MSIs but is only allocated two. In this case, you must design the Application
Layer to use only two allocated messages.
9-2
MSI Interrupts
UG-01145_avst
2015.05.04
Altera Corporation
Interrupts
- MAX 10 JTAG (15 pages)
- MAX 10 Power (21 pages)
- Unique Chip ID (12 pages)
- Remote Update IP Core (43 pages)
- Device-Specific Power Delivery Network (28 pages)
- Device-Specific Power Delivery Network (32 pages)
- Hybrid Memory Cube Controller (69 pages)
- ALTDQ_DQS IP (117 pages)
- MAX 10 Embedded Memory (71 pages)
- MAX 10 Embedded Multipliers (37 pages)
- MAX 10 Clocking and PLL (86 pages)
- MAX 10 FPGA (26 pages)
- MAX 10 FPGA (56 pages)
- USB-Blaster II (22 pages)
- GPIO (22 pages)
- LVDS SERDES (27 pages)
- User Flash Memory (33 pages)
- ALTDQ_DQS2 (100 pages)
- Avalon Tri-State Conduit Components (18 pages)
- Cyclone V Avalon-MM (166 pages)
- Cyclone III FPGA Starter Kit (36 pages)
- Cyclone V Avalon-ST (248 pages)
- Stratix V Avalon-ST (286 pages)
- Stratix V Avalon-ST (293 pages)
- DDR3 SDRAM High-Performance Controller and ALTMEMPHY IP (10 pages)
- Avalon Verification IP Suite (224 pages)
- Avalon Verification IP Suite (178 pages)
- FFT MegaCore Function (50 pages)
- DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP (140 pages)
- Floating-Point (157 pages)
- Integer Arithmetic IP (157 pages)
- Embedded Peripherals IP (336 pages)
- JESD204B IP (158 pages)
- Low Latency Ethernet 10G MAC (109 pages)
- LVDS SERDES Transmitter / Receiver (72 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (3 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (80 pages)
- IP Compiler for PCI Express (372 pages)
- Parallel Flash Loader IP (57 pages)
- Nios II C2H Compiler (138 pages)
- RAM-Based Shift Register (26 pages)
- RAM Initializer (36 pages)
- Phase-Locked Loop Reconfiguration IP Core (51 pages)
- DCFIFO (28 pages)