Altera Arria 10 Avalon-ST - Manual (Page 18)

IP Core Verification
To ensure compliance with the PCI Express specification, Altera performs extensive verification. The
simulation environment uses multiple testbenches that consist of industry-standard bus functional
models (BFMs) driving the PCI Express link interface. Altera performs the following tests in the
simulation environment:
• Directed and pseudorandom stimuli are applied to test the Application Layer interface, Configuration
Space, and all types and sizes of TLPs
• Error injection tests that inject errors in the link, TLPs, and Data Link Layer Packets (DLLPs), and
check for the proper responses
• PCI-SIG ® Compliance Checklist tests that specifically test the items in the checklist
• Random tests that test a wide range of traffic patterns
Altera provides example designs that you can leverage to test your PCBs and complete compliance base
board testing (CBB testing) at PCI-SIG, upon request.
Compatibility Testing Environment
Altera has performed significant hardware testing to ensure a reliable solution. In addition, Altera
internally tests every release with motherboards and PCI Express switches from a variety of manufac‐
turers. All PCI-SIG compliance tests are run with each IP core release.
Performance and Resource Utilization
Because the PCIe protocol stack is implemented in hardened logic, it uses no core device resources (no
ALMs and no embedded memory).
Related Information
Fitter Resources Reports
Recommended Speed Grades
Recommended speed grades are pending characterization of production Arria 10 devices.
Related Information
• Area and Timing Optimization
• Altera Software Installation and Licensing Manual
• Setting up and Running Analysis and Synthesis
Steps in Creating a Design for PCI Express
Before you begin
Select the PCIe variant that best meets your design requirements.
UG-01145_avst
2015.05.04
IP Core Verification 1-11
Datasheet Altera Corporation
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