Altera Arria 10 Avalon-ST - Manual (Page 75)

Figure 6-5: 64-Bit Avalon-ST rx_st_data Cycle Definitions for 4-Dword Header TLPs with Qword
Aligned Addresses
The following figure shows the mapping of Avalon-ST RX packets to PCI Express TLPs for TLPs for a
four dword header with qword aligned addresses with a 64-bit bus.
pld_clk
rx_st_data[63:32]
rx_st_data[31:0]
rx_st_sop
rx_st_eop
header1 header3 data1
header0 header2 data0
Figure 6-6: 64-Bit Avalon-ST rx_st_data Cycle Definitions for 4-Dword Header TLPs with Non-
Qword Addresses
The following figure shows the mapping of Avalon-ST RX packet to PCI Express TLPs for TLPs for a four
dword header with non-qword addresses with a 64-bit bus. Note that the address of the first dword is 0x4.
The address of the first enabled byte is 0xC.
pld_clk
rx_st_data[63:32]
rx_st_data[31:0]
rx_st_sop
rx_st_eop
rx_st_bar[7:0]
header1 header3 data0 data2
header0 header2 data1
10
UG-01145_avst
2015.05.04
Data Alignment and Timing for the 64‑Bit Avalon‑ST RX Interface 6-9
Interfaces and Signal Descriptions Altera Corporation
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