Altera Arria 10 Avalon-ST User Manual
Page 10

Table 1-2: Feature Comparison for all Hard IP for PCI Express IP Cores
The table compares the features of the four Hard IP for PCI Express IP Cores.
Feature
Avalon-ST Interface
Avalon-MM
Interface
Avalon-MM DMA
Avalon-ST Interface with SR-
IOV
IP Core License Free
Free
Free
Free
Native
Endpoint
Supported
Supported
Supported
Supported
Legacy
Endpoint
(1)
Supported
Not Supported
Not Supported
Not Supported
Root port
Supported
Supported
Not Supported
Not Supported
Gen1
×1, ×2, ×4, ×8
×1, ×2, ×4, ×8
Not Supported
×8
Gen2
×1, ×2, ×4, ×8
×1, ×2, ×4, ×8
×4, ×8
×4, ×8
Gen3
×1, ×2, ×4, ×8
×1, ×2, ×4
×2, ×4, ×8
×2, ×4, ×8
64-bit Applica‐
tion Layer
interface
Supported
Supported
Not supported
Not supported
128-bit
Application
Layer interface
Supported
Supported
Supported
Supported
256-bit
Application
Layer interface
Supported
Not Supported
Supported
Supported
Maximum
payload size
128, 256, 512,
1024, 2048 bytes
128, 256 bytes
128, 256 bytes
128, 256 bytes
Number of tags
supported for
non-posted
requests
256
8
16
256
(1)
Not recommended for new designs.
UG-01145_avst
2015.05.04
Arria 10 Features
1-3
Datasheet
Altera Corporation
- MAX 10 JTAG (15 pages)
- MAX 10 Power (21 pages)
- Unique Chip ID (12 pages)
- Remote Update IP Core (43 pages)
- Device-Specific Power Delivery Network (28 pages)
- Device-Specific Power Delivery Network (32 pages)
- Hybrid Memory Cube Controller (69 pages)
- ALTDQ_DQS IP (117 pages)
- MAX 10 Embedded Memory (71 pages)
- MAX 10 Embedded Multipliers (37 pages)
- MAX 10 Clocking and PLL (86 pages)
- MAX 10 FPGA (26 pages)
- MAX 10 FPGA (56 pages)
- USB-Blaster II (22 pages)
- GPIO (22 pages)
- LVDS SERDES (27 pages)
- User Flash Memory (33 pages)
- ALTDQ_DQS2 (100 pages)
- Avalon Tri-State Conduit Components (18 pages)
- Cyclone V Avalon-MM (166 pages)
- Cyclone III FPGA Starter Kit (36 pages)
- Cyclone V Avalon-ST (248 pages)
- Stratix V Avalon-ST (286 pages)
- Stratix V Avalon-ST (293 pages)
- DDR3 SDRAM High-Performance Controller and ALTMEMPHY IP (10 pages)
- Avalon Verification IP Suite (224 pages)
- Avalon Verification IP Suite (178 pages)
- FFT MegaCore Function (50 pages)
- DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP (140 pages)
- Floating-Point (157 pages)
- Integer Arithmetic IP (157 pages)
- Embedded Peripherals IP (336 pages)
- JESD204B IP (158 pages)
- Low Latency Ethernet 10G MAC (109 pages)
- LVDS SERDES Transmitter / Receiver (72 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (3 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (80 pages)
- IP Compiler for PCI Express (372 pages)
- Parallel Flash Loader IP (57 pages)
- Nios II C2H Compiler (138 pages)
- RAM-Based Shift Register (26 pages)
- RAM Initializer (36 pages)
- Phase-Locked Loop Reconfiguration IP Core (51 pages)
- DCFIFO (28 pages)