Altera Arria 10 Avalon-ST - Manual (Page 2)

Contents
Datasheet............................................................................................................. 1-1
Arria 10 Avalon-ST Interface for PCIe Datasheet...................................................................................1-1
Arria 10 Features .............................................................................................................................1-2
Release Information ....................................................................................................................................1-6
Device Family Support ...............................................................................................................................1-7
Configurations .............................................................................................................................................1-7
Arria 10 Avalon-ST Example Designs...................................................................................................... 1-9
Debug Features ..........................................................................................................................................1-10
IP Core Verification ..................................................................................................................................1-11
Compatibility Testing Environment .......................................................................................... 1-11
Performance and Resource Utilization ..................................................................................................1-11
Recommended Speed Grades ..................................................................................................................1-11
Steps in Creating a Design for PCI Express........................................................................................... 1-11
Getting Started with the Arria 10 Hard IP for PCI Express ..............................2-1
Qsys Design Flow.........................................................................................................................................2-2
Generating the Testbench ..............................................................................................................2-3
Simulating the Example Design ....................................................................................................2-3
Generating Quartus II Synthesis Files...........................................................................................2-4
Understanding the Files Generated...............................................................................................2-4
Understanding Simulation Log File Generation......................................................................... 2-4
Understanding Physical Placement of the PCIe IP Core .......................................................... 2-5
Adding Virtual Pin Assignment to the Quartus II Settings File (.qsf)..................................... 2-5
Compiling the Design in the Qsys Design Flow .........................................................................2-5
Modifying the Example Design .....................................................................................................2-7
Using the IP Catalog To Generate Your Arria 10 Hard IP for PCI Express as a Separate
Component..................................................................................................................................2-8
Files Generated for Altera IP Cores...............................................................................................2-9
Getting Started with the Configuration Space Bypass Mode Qsys Example
Design ............................................................................................................. 3-1
Copying the Configuration Space Bypass Mode Example Design .......................................................3-2
Generating the Qsys System ......................................................................................................................3-3
Generating Quartus II Synthesis Files...........................................................................................3-4
Understanding the Generated Files ..............................................................................................3-4
Understanding Simulation Log File Generation......................................................................... 3-5
Simulating the Example Design ................................................................................................................3-5
Timing for Configuration Read to Function 0 for the 256-Bit Avalon-ST Interface ............ 3-6
Timing for Configuration Write to Function 0 for the 256-Bit Avalon-ST Interface ...........3-8
Timing for Memory Write and Read of Function 1 256-Bit Avalon-ST Interface ................3-9
Partial Transcript for Configuration Space Bypass Simulation ..............................................3-11
TOC-2 Getting Started with the Arria 10 Hard IP for PCI Express with the Avalon-ST Interface
Altera Corporation