Altera Arria 10 Avalon-ST - Manual (Page 204)

The testbench has routines that perform the following tasks:
• Generates the reference clock for the Endpoint at the required frequency.
• Provides a reset at start up.
Note: Before running the testbench, you should set the following parameters:
•
serial_sim_hwtcl
: Set this parameter in _tb.v . This parameter controls
whether the testbench simulates in PIPE mode or serial mode. When is set to 0, the simulation
runs in PIPE mode; when set to 1, it runs in serial mode. Although the
serial_sim_hwtcl
parameter is available in other files, if you set this parameter at the lower level, then it will get
overwritten by the tb.v level.
•
serial_sim_hwtcl
: Set to 1 for serial simulation and 0 for PIPE simulation.
•
enable_pipe32_sim_hwtcl
: Set to 0 for serial simulation and 1 for PIPE simulation.
Chaining DMA Design Examples
This design examples shows how to create a chaining DMA native Endpoint which supports simultaneous
DMA read and write transactions. The write DMA module implements write operations from the
Endpoint memory to the root complex (RC) memory. The read DMA implements read operations from
the RC memory to the Endpoint memory.
When operating on a hardware platform, the DMA is typically controlled by a software application
running on the root complex processor. In simulation, the generated testbench, along with this design
example, provides a BFM driver module in Verilog HDL that controls the DMA operations. Because the
example relies on no other hardware interface than the PCI Express link, you can use the design example
for the initial hardware validation of your system.
The design example includes the following two main components:
• The Root Port variation
• An Application Layer design example
The end point or Root Port variant is generated in the language (Verilog HDL or VHDL) that you selected
for the variation file. The testbench files are only generated in Verilog HDL in the current release. If you
choose to use VHDL for your variant, you must have a mixed-language simulator to run this testbench.
Note: The chaining DMA design example requires setting BAR 2 or BAR 3 to a minimum of 256 bytes.
To run the DMA tests using MSI, you must set the Number of MSI messages requested parameter
under the PCI Express/PCI Capabilities page to at least 2.
The chaining DMA design example uses an architecture capable of transferring a large amount of
fragmented memory without accessing the DMA registers for every memory block. For each block of
memory to be transferred, the chaining DMA design example uses a descriptor table containing the
following information:
• Length of the transfer
• Address of the source
• Address of the destination
• Control bits to set the handshaking behavior between the software application or BFM driver and the
chaining DMA module
17-4 Chaining DMA Design Examples
UG-01145_avst
2015.05.04
Altera Corporation Testbench and Design Example
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