Freescale Semiconductor DSP56366 - Manual (Page 56)

Timer
DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4
2-22 Freescale Semiconductor
2.12 Timer
2.13 JTAG/OnCE Interface
Table 2-14 Timer Signal
Signal
Name
Type
State during
Reset
Signal Description
TIO0 Input or
Output
Input Timer 0 Schmitt-Trigger Input/Output — When timer 0 functions as an
external event counter or in measurement mode, TIO0 is used as input.
When timer 0 functions in watchdog, timer, or pulse modulation mode,
TIO0 is used as output.
The default mode after reset is GPIO input. This can be changed to
output or configured as a timer input/output through the timer 0
control/status register (TCSR0). If TIO0 is not being used, it is
recommended to either define it as GPIO output immediately at the
beginning of operation or leave it defined as GPIO input but connected
to Vcc through a pull-up resistor in order to ensure a stable logic level at
this input.
This input is 5 V tolerant.
Table 2-15 JTAG/OnCE Interface
Signal
Name
Signal
Type
State during
Reset
Signal Description
TCK Input Input Test Clock — TCK is a test clock input signal used to synchronize the JTAG
test logic. It has an internal pull-up resistor.
This input is 5 V tolerant.
TDI Input Input Test Data Input — TDI is a test data serial input signal used for test
instructions and data. TDI is sampled on the rising edge of TCK and has an
internal pull-up resistor.
This input is 5 V tolerant.
TDO Output Tri-stated Test Data Output — TDO is a test data serial output signal used for test
instructions and data. TDO is tri-statable and is actively driven in the shift-IR
and shift-DR controller states. TDO changes on the falling edge of TCK.
TMS Input Input Test Mode Select — TMS is an input signal used to sequence the test
controller’s state machine. TMS is sampled on the rising edge of TCK and has
an internal pull-up resistor.
This input is 5 V tolerant.