Esai – Freescale Semiconductor DSP56366 User Manual
Page 338
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Programming Sheets
DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4
D-30
Freescale Semiconductor
Figure D-15. ESAI Transmit Clock Control Register
Application:
Date:
Programmer:
15
6
5
4
19
18
17
16
10
9
8
7
14
13
12
11
TPM0
32
10
TPM2
23
22
21
20
TP
M
1
TP
M
3
TPM4
TPM5
TP
M
6
TPM7
TP
S
R
TDC0
TDC1
TDC2
TD
C3
TDC4
TF
P
0
TF
P
1
TFP2
TFP3
TCK
P
TFS
P
THCK
P
TCKD
TFSD
THCK
D
TCKP
Descrip
tio
n
0
1
Tr
ansmitter
Clo
ck Pola
rity set to clo
ckout on r
ising edge of
transmit clock, latch in on
falling edge o
f transmit clock.
Tr
ansmitter
Clo
ck Pola
rity set to
clo
ckout on fa
lling e
dge of
T
F
SP
Descrip
tio
n
0
1
Fra
m
e sync polarity po
sitive
Fra
m
e sync polarity ne
gative
TF
P [3:0
]
De
scripti
on
Sets divide rate for transmission
TCK
D
Descrip
tio
n
0
1
External clock sour
ce
used
Inter
nal clock source
TF
SD
Des
criptio
n
0
1
F
S
T is input
F
S
T is ou
tput
THC
K
D
D
es
criptio
n
0
1
HCKT
is input
HCKT
is output
T
HCKP
D
escript
ion
0
1
T
ransmitter High F
requency Clock Polarity set to clockout
Tra
nsmitter H
igh F
requ
ency Clock
Polarity set t
o clockout
Ra
nge $0 -
$F (
1 -16)
. See 8.3.1.4
T
DC [
4:0]
D
e
scripti
on
Divider
contr
ol. Range $00
- $F
F (1
- 32)
See 8.3.1.
3
TPM [
7:0]
D
e
scripti
on
S
p
ecifie
s the
prescaler
divid
e rate is
tran
smitter clock gener
ator
TPSR
Descript
ion
0
1
Divide b
y 8 pr
escaler op
erational
Divide b
y 8 pr
escaler bypassed
Range fr
om $00 -
$FF (
1 - 2
56).
AA
1777
for the
S
e
e 8.3.1.1
ESAI
T
CCR - E
S
AI Tran
smit Clock Con
trol Regis
ter
X: $FFFF
B6 Reset: $000000
transmit clock, latch in on ri
sing ed
ge of tran
smit clock
on r
ising edge of t
ransmit clock, latch
in on
fallin
g edge
on falling ed
ge of tra
nsmit clock, latch in on rising
edge
high fr
equency clock