Freescale Semiconductor DSP56366 Instruction Manuals and User Guides
We have 1 Instruction Manual and User Guide for DSP56366 Freescale Semiconductor
Manuals 
| Recognized languages: | English |
|---|---|
| Pages: | 366 |
| Size: | 3.54 MB |
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Document Outline
- DSP56366 User Manual
- Contact Information
- Contents
- 1 DSP56366 Overview
- 1.1 Introduction
- 1.2 DSP56300 Core Description
- 1.3 DSP56366 Audio Processor Architecture
- 1.4 DSP56300 Core Functional Blocks
- 1.5 Peripheral Overview
- 2 Signal/Connection Descriptions
- 2.1 Signal Groupings
- 2.2 Power
- 2.3 Ground
- 2.4 Clock and PLL
- 2.5 External Memory Expansion Port (Port A)
- 2.6 Interrupt and Mode Control
- 2.7 PARALLEL HOST INTERFACE (HDI08)
- 2.8 Serial Host Interface
- 2.9 Enhanced Serial Audio Interface
- 2.10 Enhanced Serial Audio Interface_1
- 2.11 SPDIF Transmitter Digital Audio Interface
- 2.12 Timer
- 2.13 JTAG/OnCE Interface
- 3 Memory Configuration
- 4 Core Configuration
- 5 General Purpose Input/Output
- 6 Host Interface (HDI08)
- 6.1 Introduction
- 6.2 HDI08 Features
- 6.3 HDI08 Host Port Signals
- 6.4 HDI08 Block Diagram
- 6.5 HDI08 - DSP-Side Programmer’s Model
- 6.5.1 Host Receive Data Register (HORX)
- 6.5.2 Host Transmit Data Register (HOTX)
- 6.5.3 Host Control Register (HCR)
- 6.5.3.1 HCR Host Receive Interrupt Enable (HRIE) Bit 0
- 6.5.3.2 HCR Host Transmit Interrupt Enable (HTIE) Bit 1
- 6.5.3.3 HCR Host Command Interrupt Enable (HCIE) Bit 2
- 6.5.3.4 HCR Host Flags 2,3 (HF2,HF3) Bits 3-4
- 6.5.3.5 HCR Host DMA Mode Control Bits (HDM0, HDM1, HDM2) Bits 5-7
- 6.5.3.6 HCR Reserved Bits 8-15
- 6.5.4 Host Status Register (HSR)
- 6.5.5 Host Base Address Register (HBAR)
- 6.5.6 Host Port Control Register (HPCR)
- 6.5.6.1 HPCR Host GPIO Port Enable (HGEN) Bit 0
- 6.5.6.2 HPCR Host Address Line 8 Enable (HA8EN) Bit 1
- 6.5.6.3 HPCR Host Address Line 9 Enable (HA9EN) Bit 2
- 6.5.6.4 HPCR Host Chip Select Enable (HCSEN) Bit 3
- 6.5.6.5 HPCR Host Request Enable (HREN) Bit 4
- 6.5.6.6 HPCR Host Acknowledge Enable (HAEN) Bit 5
- 6.5.6.7 HPCR Host Enable (HEN) Bit 6
- 6.5.6.8 HPCR Reserved Bit 7
- 6.5.6.9 HPCR Host Request Open Drain (HROD) Bit 8
- 6.5.6.10 HPCR Host Data Strobe Polarity (HDSP) Bit 9
- 6.5.6.11 HPCR Host Address Strobe Polarity (HASP) Bit 10
- 6.5.6.12 HPCR Host Multiplexed bus (HMUX) Bit 11
- 6.5.6.13 HPCR Host Dual Data Strobe (HDDS) Bit 12
- 6.5.6.14 HPCR Host Chip Select Polarity (HCSP) Bit 13
- 6.5.6.15 HPCR Host Request Polarity (HRP) Bit 14
- 6.5.6.16 HPCR Host Acknowledge Polarity (HAP) Bit 15
- 6.5.7 Data direction register (HDDR)
- 6.5.8 Host Data Register (HDR)
- 6.5.9 DSP-Side Registers After Reset
- 6.5.10 Host Interface DSP Core Interrupts
- 6.6 HDI08 - External Host Programmer’s Model
- 6.6.1 Interface Control Register (ICR)
- 6.6.2 Command Vector Register (CVR)
- 6.6.3 Interface Status Register (ISR)
- 6.6.4 Interrupt Vector Register (IVR)
- 6.6.5 Receive Byte Registers (RXH:RXM:RXL)
- 6.6.6 Transmit Byte Registers (TXH:TXM:TXL)
- 6.6.7 Host Side Registers After Reset
- 6.6.8 General Purpose INPUT/OUTPUT (GPIO)
- 6.7 Servicing The Host Interface
- 7 Serial Host Interface
- 7.1 Introduction
- 7.2 Serial Host Interface Internal Architecture
- 7.3 SHI Clock Generator
- 7.4 Serial Host Interface Programming Model
- 7.4.1 SHI Input/Output Shift Register (IOSR)-Host Side
- 7.4.2 SHI Host Transmit Data Register (HTX)-DSP Side
- 7.4.3 SHI Host Receive Data FIFO (HRX)-DSP Side
- 7.4.4 SHI Slave Address Register (HSAR)-DSP Side
- 7.4.5 SHI Clock Control Register (HCKR)-DSP Side
- 7.4.6 SHI Control/Status Register (HCSR)-DSP Side
- 7.4.6.1 HCSR Host Enable (HEN)-Bit 0
- 7.4.6.2 HCSR I2C/SPI Selection (HI2C)-Bit 1
- 7.4.6.3 HCSR Serial Host Interface Mode (HM[1:0])-Bits 3-2
- 7.4.6.4 HCSR I2C Clock Freeze (HCKFR)-Bit 4
- 7.4.6.5 HCSR FIFO-Enable Control (HFIFO)-Bit 5
- 7.4.6.6 HCSR Master Mode (HMST)-Bit 6
- 7.4.6.7 HCSR Host-Request Enable (HRQE[1:0])-Bits 8-7
- 7.4.6.8 HCSR Idle (HIDLE)-Bit 9
- 7.4.6.9 HCSR Bus-Error Interrupt Enable (HBIE)-Bit 10
- 7.4.6.10 HCSR Transmit-Interrupt Enable (HTIE)-Bit 11
- 7.4.6.11 HCSR Receive Interrupt Enable (HRIE[1:0])-Bits 13-12
- 7.4.6.12 HCSR Host Transmit Underrun Error (HTUE)-Bit 14
- 7.4.6.13 HCSR Host Transmit Data Empty (HTDE)-Bit 15
- 7.4.6.14 HCSR Reserved Bits-Bits 23, 18 and 16
- 7.4.6.15 Host Receive FIFO Not Empty (HRNE)-Bit 17
- 7.4.6.16 Host Receive FIFO Full (HRFF)-Bit 19
- 7.4.6.17 Host Receive Overrun Error (HROE)-Bit 20
- 7.4.6.18 Host Bus Error (HBER)-Bit 21
- 7.4.6.19 HCSR Host Busy (HBUSY)-Bit 22
- 7.5 Characteristics Of The SPI Bus
- 7.6 Characteristics Of The I2C Bus
- 7.7 SHI Programming Considerations
- 8 Enhanced Serial AUDIO Interface (ESAI)
- 8.1 Introduction
- 8.2 ESAI Data and Control Pins
- 8.2.1 Serial Transmit 0 Data Pin (SDO0)
- 8.2.2 Serial Transmit 1 Data Pin (SDO1)
- 8.2.3 Serial Transmit 2/Receive 3 Data Pin (SDO2/SDI3)
- 8.2.4 Serial Transmit 3/Receive 2 Data Pin (SDO3/SDI2)
- 8.2.5 Serial Transmit 4/Receive 1 Data Pin (SDO4/SDI1)
- 8.2.6 Serial Transmit 5/Receive 0 Data Pin (SDO5/SDI0)
- 8.2.7 Receiver Serial Clock (SCKR)
- 8.2.8 Transmitter Serial Clock (SCKT)
- 8.2.9 Frame Sync for Receiver (FSR)
- 8.2.10 Frame Sync for Transmitter (FST)
- 8.2.11 High Frequency Clock for Transmitter (HCKT)
- 8.2.12 High Frequency Clock for Receiver (HCKR)
- 8.3 ESAI Programming Model
- 8.3.1 ESAI Transmitter Clock Control Register (TCCR)
- 8.3.1.1 TCCR Transmit Prescale Modulus Select (TPM7-TPM0) - Bits 0-7
- 8.3.1.2 TCCR Transmit Prescaler Range (TPSR) - Bit 8
- 8.3.1.3 TCCR Tx Frame Rate Divider Control (TDC4-TDC0) - Bits 9-13
- 8.3.1.4 TCCR Tx High Frequency Clock Divider (TFP3-TFP0) - Bits 14-17
- 8.3.1.5 TCCR Transmit Clock Polarity (TCKP) - Bit 18
- 8.3.1.6 TCCR Transmit Frame Sync Polarity (TFSP) - Bit 19
- 8.3.1.7 TCCR Transmit High Frequency Clock Polarity (THCKP) - Bit 20
- 8.3.1.8 TCCR Transmit Clock Source Direction (TCKD) - Bit 21
- 8.3.1.9 TCCR Transmit Frame Sync Signal Direction (TFSD) - Bit 22
- 8.3.1.10 TCCR Transmit High Frequency Clock Direction (THCKD) - Bit 23
- 8.3.2 ESAI Transmit Control Register (TCR)
- 8.3.2.1 TCR ESAI Transmit 0 Enable (TE0) - Bit 0
- 8.3.2.2 TCR ESAI Transmit 1 Enable (TE1) - Bit 1
- 8.3.2.3 TCR ESAI Transmit 2 Enable (TE2) - Bit 2
- 8.3.2.4 TCR ESAI Transmit 3 Enable (TE3) - Bit 3
- 8.3.2.5 TCR ESAI Transmit 4 Enable (TE4) - Bit 4
- 8.3.2.6 TCR ESAI Transmit 5 Enable (TE5) - Bit 5
- 8.3.2.7 TCR Transmit Shift Direction (TSHFD) - Bit 6
- 8.3.2.8 TCR Transmit Word Alignment Control (TWA) - Bit 7
- 8.3.2.9 TCR Transmit Network Mode Control (TMOD1-TMOD0) - Bits 8-9
- 8.3.2.10 TCR Tx Slot and Word Length Select (TSWS4-TSWS0) - Bits 10-14
- 8.3.2.11 TCR Transmit Frame Sync Length (TFSL) - Bit 15
- 8.3.2.12 TCR Transmit Frame Sync Relative Timing (TFSR) - Bit 16
- 8.3.2.13 TCR Transmit Zero Padding Control (PADC) - Bit 17
- 8.3.2.14 TCR Reserved Bit - Bits 18
- 8.3.2.15 TCR Transmit Section Personal Reset (TPR) - Bit 19
- 8.3.2.16 TCR Transmit Exception Interrupt Enable (TEIE) - Bit 20
- 8.3.2.17 TCR Transmit Even Slot Data Interrupt Enable (TEDIE) - Bit 21
- 8.3.2.18 TCR Transmit Interrupt Enable (TIE) - Bit 22
- 8.3.2.19 TCR Transmit Last Slot Interrupt Enable (TLIE) - Bit 23
- 8.3.3 ESAI Receive Clock Control Register (RCCR)
- 8.3.3.1 RCCR Receiver Prescale Modulus Select (RPM7-RPM0) - Bits 7-0
- 8.3.3.2 RCCR Receiver Prescaler Range (RPSR) - Bit 8
- 8.3.3.3 RCCR Rx Frame Rate Divider Control (RDC4-RDC0) - Bits 9-13
- 8.3.3.4 RCCR Rx High Frequency Clock Divider (RFP3-RFP0) - Bits 14-17
- 8.3.3.5 RCCR Receiver Clock Polarity (RCKP) - Bit 18
- 8.3.3.6 RCCR Receiver Frame Sync Polarity (RFSP) - Bit 19
- 8.3.3.7 RCCR Receiver High Frequency Clock Polarity (RHCKP) - Bit 20
- 8.3.3.8 RCCR Receiver Clock Source Direction (RCKD) - Bit 21
- 8.3.3.9 RCCR Receiver Frame Sync Signal Direction (RFSD) - Bit 22
- 8.3.3.10 RCCR Receiver High Frequency Clock Direction (RHCKD) - Bit 23
- 8.3.4 ESAI Receive Control Register (RCR)
- 8.3.4.1 RCR ESAI Receiver 0 Enable (RE0) - Bit 0
- 8.3.4.2 RCR ESAI Receiver 1 Enable (RE1) - Bit 1
- 8.3.4.3 RCR ESAI Receiver 2 Enable (RE2) - Bit 2
- 8.3.4.4 RCR ESAI Receiver 3 Enable (RE3) - Bit 3
- 8.3.4.5 RCR Reserved Bits - Bits 4-5, 17-18
- 8.3.4.6 RCR Receiver Shift Direction (RSHFD) - Bit 6
- 8.3.4.7 RCR Receiver Word Alignment Control (RWA) - Bit 7
- 8.3.4.8 RCR Receiver Network Mode Control (RMOD1-RMOD0) - Bits 8-9
- 8.3.4.9 RCR Receiver Slot and Word Select (RSWS4-RSWS0) - Bits 10-14
- 8.3.4.10 RCR Receiver Frame Sync Length (RFSL) - Bit 15
- 8.3.4.11 RCR Receiver Frame Sync Relative Timing (RFSR) - Bit 16
- 8.3.4.12 RCR Receiver Section Personal Reset (RPR) - Bit 19
- 8.3.4.13 RCR Receive Exception Interrupt Enable (REIE) - Bit 20
- 8.3.4.14 RCR Receive Even Slot Data Interrupt Enable (REDIE) - Bit 21
- 8.3.4.15 RCR Receive Interrupt Enable (RIE) - Bit 22
- 8.3.4.16 RCR Receive Last Slot Interrupt Enable (RLIE) - Bit 23
- 8.3.5 ESAI Common Control Register (SAICR)
- 8.3.5.1 SAICR Serial Output Flag 0 (OF0) - Bit 0
- 8.3.5.2 SAICR Serial Output Flag 1 (OF1) - Bit 1
- 8.3.5.3 SAICR Serial Output Flag 2 (OF2) - Bit 2
- 8.3.5.4 SAICR Reserved Bits - Bits 3-5, 9-23
- 8.3.5.5 SAICR Synchronous Mode Selection (SYN) - Bit 6
- 8.3.5.6 SAICR Transmit External Buffer Enable (TEBE) - Bit 7
- 8.3.5.7 SAICR Alignment Control (ALC) - Bit 8
- 8.3.6 ESAI Status Register (SAISR)
- 8.3.6.1 SAISR Serial Input Flag 0 (IF0) - Bit 0
- 8.3.6.2 SAISR Serial Input Flag 1 (IF1) - Bit 1
- 8.3.6.3 SAISR Serial Input Flag 2 (IF2) - Bit 2
- 8.3.6.4 SAISR Reserved Bits - Bits 3-5, 11-12, 18-23
- 8.3.6.5 SAISR Receive Frame Sync Flag (RFS) - Bit 6
- 8.3.6.6 SAISR Receiver Overrun Error Flag (ROE) - Bit 7
- 8.3.6.7 SAISR Receive Data Register Full (RDF) - Bit 8
- 8.3.6.8 SAISR Receive Even-Data Register Full (REDF) - Bit 9
- 8.3.6.9 SAISR Receive Odd-Data Register Full (RODF) - Bit 10
- 8.3.6.10 SAISR Transmit Frame Sync Flag (TFS) - Bit 13
- 8.3.6.11 SAISR Transmit Underrun Error Flag (TUE) - Bit 14
- 8.3.6.12 SAISR Transmit Data Register Empty (TDE) - Bit 15
- 8.3.6.13 SAISR Transmit Even-Data Register Empty (TEDE) - Bit 16
- 8.3.6.14 SAISR Transmit Odd-Data Register Empty (TODE) - Bit 17
- 8.3.7 ESAI Receive Shift Registers
- 8.3.8 ESAI Receive Data Registers (RX3, RX2, RX1, RX0)
- 8.3.9 ESAI Transmit Shift Registers
- 8.3.10 ESAI Transmit Data Registers (TX5, TX4, TX3, TX2,TX1,TX0)
- 8.3.11 ESAI Time Slot Register (TSR)
- 8.3.12 Transmit Slot Mask Registers (TSMA, TSMB)
- 8.3.13 Receive Slot Mask Registers (RSMA, RSMB)
- 8.3.1 ESAI Transmitter Clock Control Register (TCCR)
- 8.4 Operating Modes
- 8.5 GPIO - Pins and Registers
- 8.6 ESAI Initialization Examples
- 9 Enhanced Serial Audio Interface 1 (ESAI_1)
- 9.1 Introduction
- 9.2 ESAI_1 Data and Control Pins
- 9.2.1 Serial Transmit 0 Data Pin (SDO0_1)
- 9.2.2 Serial Transmit 1 Data Pin (SDO1_1)
- 9.2.3 Serial Transmit 2/Receive 3 Data Pin (SDO2_1/SDI3_1)
- 9.2.4 Serial Transmit 3/Receive 2 Data Pin (SDO3_1/SDI2_1)
- 9.2.5 Serial Transmit 4/Receive 1 Data Pin (SDO4_1/SDI1_1)
- 9.2.6 Serial Transmit 5/Receive 0 Data Pin (SDO5_1/SDI0_1)
- 9.2.7 Receiver Serial Clock (SCKR_1)
- 9.2.8 Transmitter Serial Clock (SCKT_1)
- 9.2.9 Frame Sync for Receiver (FSR_1)
- 9.2.10 Frame Sync for Transmitter (FST_1)
- 9.3 ESAI_1 Programming Model
- 9.3.1 ESAI_1 Multiplex Control Register (EMUXR)
- 9.3.2 ESAI_1 Transmitter Clock Control Register (TCCR_1)
- 9.3.3 ESAI_1 Transmit Control Register (TCR_1)
- 9.3.4 ESAI_1 Receive Clock Control Register (RCCR_1)
- 9.3.5 ESAI_1 Receive Control Register (RCR_1)
- 9.3.6 ESAI_1 Common Control Register (SAICR_1)
- 9.3.7 ESAI_1 Status Register (SAISR_1)
- 9.3.8 ESAI_1 Receive Shift Registers
- 9.3.9 ESAI_1 Receive Data Registers
- 9.3.10 ESAI_1 Transmit Shift Registers
- 9.3.11 ESAI_1 Transmit Data Registers
- 9.3.12 ESAI_1 Time Slot Register (TSR_1)
- 9.3.13 Transmit Slot Mask Registers (TSMA_1, TSMB_1)
- 9.3.14 Receive Slot Mask Registers (RSMA_1, RSMB_1)
- 9.4 Operating Modes
- 9.5 GPIO - Pins and Registers
- 10 Digital Audio Transmitter
- 10.1 Introduction
- 10.2 DAX Signals
- 10.3 DAX Functional Overview
- 10.4 DAX Programming Model
- 10.5 DAX Internal Architecture
- 10.5.1 DAX Audio Data Register (XADR)
- 10.5.2 DAX Audio Data Buffers (XADBUFA / XADBUFB)
- 10.5.3 DAX Audio Data Shift Register (XADSR)
- 10.5.4 DAX Non-Audio Data Register (XNADR)
- 10.5.4.1 DAX Channel A Validity (XVA)-Bit 10
- 10.5.4.2 DAX Channel A User Data (XUA)-Bit 11
- 10.5.4.3 DAX Channel A Channel Status (XCA)-Bit 12
- 10.5.4.4 DAX Channel B Validity (XVB)-Bit 13
- 10.5.4.5 DAX Channel B User Data (XUB)-Bit 14
- 10.5.4.6 DAX Channel B Channel Status (XCB)-Bit 15
- 10.5.4.7 XNADR Reserved Bits-Bits 0-9, 16-23
- 10.5.5 DAX Non-Audio Data Buffer (XNADBUF)
- 10.5.6 DAX Control Register (XCTR)
- 10.5.7 DAX Status Register (XSTR)
- 10.5.8 DAX Parity Generator (PRTYG)
- 10.5.9 DAX Biphase Encoder
- 10.5.10 DAX Preamble Generator
- 10.5.11 DAX Clock Multiplexer
- 10.5.12 DAX State Machine
- 10.6 DAX Programming Considerations
- 10.7 GPIO (PORT D) - Pins and Registers
- 11 Timer/ Event Counter
- 11.1 Introduction
- 11.2 Timer/Event Counter Architecture
- 11.3 Timer/Event Counter Programming Model
- 11.3.1 Prescaler Counter
- 11.3.2 Timer Prescaler Load Register (TPLR)
- 11.3.3 Timer Prescaler Count Register (TPCR)
- 11.3.4 Timer Control/Status Register (TCSR)
- 11.3.4.1 TCSR Timer Enable (TE) Bit 0
- 11.3.4.2 TCSR Timer Overflow Interrupt Enable (TOIE) Bit 1
- 11.3.4.3 TCSR Timer Compare Interrupt Enable (TCIE) Bit 2
- 11.3.4.4 TCSR Timer Control (TC[3:0]) Bits 4-7
- 11.3.4.5 TCSR Inverter (INV) Bit 8
- 11.3.4.6 TCSR Timer Reload Mode (TRM) Bit 9
- 11.3.4.7 TCSR Direction (DIR) Bit 11
- 11.3.4.8 TCSR Data Input (DI) Bit 12
- 11.3.4.9 TCSR Data Output (DO) Bit 13
- 11.3.4.10 TCSR Prescaler Clock Enable (PCE) Bit 15
- 11.3.4.11 TCSR Timer Overflow Flag (TOF) Bit 20
- 11.3.4.12 TCSR Timer Compare Flag (TCF) Bit 21
- 11.3.4.13 TCSR Reserved Bits (Bits 3, 10, 14, 16-19, 22, 23)
- 11.3.5 Timer Load Register (TLR)
- 11.3.6 Timer Compare Register (TCPR)
- 11.3.7 Timer Count Register (TCR)
- 11.4 Timer Modes of Operation
- Index