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6 pll initialization, 1 pll multiplication factor (mf0-mf11), 2 pll pre-divider factor (pd0-pd3) – Freescale Semiconductor DSP56366 User Manual

Page 87: 3 crystal range bit (xtlr), 4 xtal disable bit (xtld), 7 device identification (id) register, 8 jtag identification (id) register, Pll initialization -13, Pll multiplication factor (mf0-mf11) -13, Pll pre-divider factor (pd0-pd3) -13

6 pll initialization, 1 pll multiplication factor (mf0-mf11), 2 pll pre-divider factor (pd0-pd3) | 3 crystal range bit (xtlr), 4 xtal disable bit (xtld), 7 device identification (id) register, 8 jtag identification (id) register, Pll initialization -13, Pll multiplication factor (mf0-mf11) -13, Pll pre-divider factor (pd0-pd3) -13 | Freescale Semiconductor DSP56366 User Manual | Page 87 / 366 6 pll initialization, 1 pll multiplication factor (mf0-mf11), 2 pll pre-divider factor (pd0-pd3) | 3 crystal range bit (xtlr), 4 xtal disable bit (xtld), 7 device identification (id) register, 8 jtag identification (id) register, Pll initialization -13, Pll multiplication factor (mf0-mf11) -13, Pll pre-divider factor (pd0-pd3) -13 | Freescale Semiconductor DSP56366 User Manual | Page 87 / 366