Comtech EF Data SDM-300L3 - Manual (Page 13)

SDM-300L3 Satellite Modem Revision 1
Preface MN/SDM300L3.IOM
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Figures
Figure 1-1. Block Diagram........................................................................................................................1–2
Figure 1-2. Demodulator Block Diagram ................................................................................................1–10
Figure 1-3. M&C Block Diagram.............................................................................................................1–13
Figure 1-4. Dimensional Envelope Drawing...........................................................................................1–15
Figure 2-1. Installation of the Optional Mounting Bracket KT/6228-1 ......................................................2–3
Figure 2-2. Overhead Interface PCB Installation .....................................................................................2–5
Figure 2-3. Reed-Solomon Codec Installation .........................................................................................2–7
Figure 2-4. Turbo Codec Installation ......................................................................................................2–10
Figure 2-5. Data I/O Connector (J8) Removal/Installation .....................................................................2–13
Figure 2-6. Overhead Board with Field-Changeable Chips ...................................................................2–15
Figure 2-7. Main Board Field-Changeable Chips (Shown with Overhead Card Removed)...................2–15
Figure 3-1. SDM-300L3 Rear Panel.........................................................................................................3–2
Figure 4-1. Front Panel View....................................................................................................................4–1
Figure 4-2. Keypad ...................................................................................................................................4–3
Figure 4-3. Menu Tree..............................................................................................................................4–6
Figure 4-4. RF Loopback........................................................................................................................4–21
Figure 4-5. IF Loopback .........................................................................................................................4–22
Figure 4-6. Baseband Loopback ............................................................................................................4–30
Figure 4-7. Interface Loopback ..............................................................................................................4–31
Figure 6-1. EIA-422, EIA-232, or V.35 Master/Master Clocking Diagram................................................6–4
Figure 6-2. EIA-422, EIA-232, or V.35 Master/Slave Clocking Diagram..................................................6–5
Figure 6-3. IDR/IBS G.703 Master/Master Clocking Diagram..................................................................6–6
Figure 6-4. IDR/IBS G.703 Master/Slave Clocking Diagram....................................................................6–7
Figure 6-5. D&I G.703 Master/Master Clocking Diagram.........................................................................6–8
Figure 6-6. Clock Slip .............................................................................................................................6–10
Figure 6-7. Doppler Shift ........................................................................................................................6–11
Figure 6-8. Transmit Section of the Asymmetrical Loop Timing Block Diagram....................................6–15
Figure 6-9. Receive Section of the Asymmetrical Loop Timing Block Diagram.....................................6–16
Figure 7-1. Viterbi Decoder ......................................................................................................................7–7
Figure 7-2. Viterbi Decoder and Reed-Solomon ......................................................................................7–8
Figure 7-3. BPSK and (O)QPSK BER Performance ................................................................................7–9
Figure 7-4. Turbo Product Codec...........................................................................................................7–10
Figure 7-5. Sequential Decoder, Reed-Solomon, and 1544 kbps .........................................................7–11
Figure 7-6. Sequential Decoder and 56 kbps.........................................................................................7–12
Figure 7-7. Sequential Decoder and 1544 kbps.....................................................................................7–13
Figure 8-1. Fault Isolation Test Setup ......................................................................................................8–2
Figure 8-2. Typical Output Spectrum .......................................................................................................8–5
Figure 8-3. Typical Eye Constellations.....................................................................................................8–6
Figure 9-1. SDM-300L Fault Tree ............................................................................................................9–3
Figure 10-1. IBS Interface Block Diagram..............................................................................................10–3
Figure 10-2. IDR Interface Block Diagram .............................................................................................10–7
Figure 10-3. D&I with Asynchronous Overhead Data Flow..................................................................10–10
Figure 10-4. E1 Framing Formats ........................................................................................................10–15
Figure 10-5. T1 Framing Formats ........................................................................................................10–16
Figure 11-1. ASYNC/AUPC Block Diagram ...........................................................................................11–3
Figure 11-2. Remote ASYNC Connection Diagram for Y-Cable..........................................................11–13
Figure 11-3. Remote ASYNC Connection Diagram for Breakout Panel ..............................................11–13
Figure 14-1. Block Diagram....................................................................................................................14–2
Figure 14-2. Carrier Level vs Symbol Rate ..........................................................................................14–21