Comtech EF Data SDM-650B - Manual (Page 129)

SDM-650B Satellite Modem Theory of Operation
Rev. 6 5–5
5.1.2 Theory of Operation
Data that is to be transmitted is input to the digital interface of the modulator. The format
is RS-422, and includes a clock synchronous with the data. The data at this point is clean
and dejittered.
A data rate clock provided by the clock synthesizer and buffered by the digital interface
is output from the card. The frequency of this clock is programmable. The use of this
clock as the source timing signal for the link is optional.
In addition to these functions, the digital interface provides buffering of M&C signals to
the microcomputer data bus. The data for all programmable functions passes across this
interface, as well as module fault information from the modulator back to the M&C.
Faults reported include:
• Synthesizers
out-of-lock
• AGC level
• Input data clock activity
• Digital I and Q channel fault
The data is delivered from the data interface to the differential encoder, and then to the
scrambler. The differential encoder is a 2-bit encoder which allows for resolution of two
of the four ambiguity states of the QPSK demodulator, or of both states of a BPSK
demodulator.
The differential encoder is programmable to ON or OFF.
The scrambler is designed according to CCITT V.35. The scrambler provides a pseudo-
random characteristic to the data stream for dispersal of the transmitted energy,
independent of the data pattern.
The scrambler is programmable ON or OFF.
The data then passes to the convolutional encoder. The convolutional encoder generates
the parity bits from the input data stream that allows for error correction at the far end of
the link.
The rate of the encoder may be:
• 7/8
• 3/4
• 1/2