Altera Serial Digital Interface (SDI) MegaCore Function - Manual (Page 92)

4–4 Chapter 4: SDI Audio IP Cores
SDI Audio Embed MegaCore Function
Serial Digital Interface (SDI) MegaCore Function February 2013 Altera Corporation
User Guide
Signals
Table 4–2 lists the general input and output signals for the SDI Audio Embed
MegaCore function.
Table 4–3 lists the video input and output signals for the SDI Audio Embed
MegaCore function.
Table 4–2. General Input and Output Signals
Signal Width Direction Description
reset [0:0] Input This signal resets the system.
fix_clk [0:0] Input
This signal provides the frequency reference used when
detecting the difference between video standards using 1 and
1/1.001 clock rates. If its frequency is 0, the signal only
detects either one of the clock rates.
The core limits the possible frequencies for this signal to
24.576 MHz, 25 MHz, 50 MHz, 100 MHz, and 200 MHz. Set
the required frequency using the Frequency of fix_clk
parameter.
vid_std_rate [0:0] Input
If you set the Frequency of fix_clk parameter to 0, you must
drive this signal high to detect a video frame rate of 1/1.001
and low to detect a video frame rate of 1. For other settings of
the Frequency of fix_clk parameter, the core automatically
detects these frame rates and drives this signal low.
vid_clk48 [0:0] Output
The 48 kHz output clock that is synchronous to the video.
This clock signal is only available when you turn on the
Frequency Sine Wave Generator or Include Clock
parameter.
Table 4–3. Video Input and Output Signals (Part 1 of 2)
Signal Bits Direction Description
vid_clk [0:0] Input
The video clock that is typically 27 MHz for SD-SDI,
74.25 MHz or 74.17 MHz for HD-SDI, or 148.5 MHz
or 148.35 MHz for 3G-SDI standards. You can use
higher clock rates with the vid_datavalid signal.
vid_std [1:0] Input
Set this signal to indicate the following formats:
■ [00] for10-bit SD-SDI
■ [01] for 20-bit HD-SDI
■ [10] for 3G-SDI Level B
■ [11] for 3G-SDI Level A
vid_datavalid [0:0] Input Assert this signal when the video data is valid.