Altera Serial Digital Interface (SDI) MegaCore Function User Manual
Page 60

3–30
Chapter 3: Functional Description
Block Description
Serial Digital Interface (SDI) MegaCore Function
February 2013
Altera Corporation
User Guide
shows a flow chart of the SDI dynamic reconfiguration process for
transceiver-based devices.
Figure 3–18. Dynamic Reconfiguration Process Flow for Transceiver-based Devices
Notes to
(1) SDI MegaCore (Receiver/Duplex) asserts rx_analogreset and rx_digitalreset signals to transceiver when the
transceiver is being reconfigured.
(2) The rx_analogreset signal deasserts when the transceiver is completely reconfigured, and rx_digitalreset
signal deasserts when rx_pll is stable.
Normal Operation
Reconfiguration
in Process
Data
Rate Change?
Reconfiguration
Done?
No
Yes
Yes
Start DPRIO
Idle
Write to ALT2GXB
ALT2GXB_RECONFIG
Busy?
Last ROM
Address?
No
No
No
Yes
Yes
Reconfiguration
Done
Reconfiguration
in Process
SDI_START_RECONFIG
SDI_RECONFIG_DONE
SDI MegaCore (Receiver/Duplex)
ALT2GXB_RECONFIG Control Logic
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- MAX 10 Power (21 pages)
- Unique Chip ID (12 pages)
- Remote Update IP Core (43 pages)
- Device-Specific Power Delivery Network (28 pages)
- Device-Specific Power Delivery Network (32 pages)
- Hybrid Memory Cube Controller (69 pages)
- ALTDQ_DQS IP (117 pages)
- MAX 10 Embedded Memory (71 pages)
- MAX 10 Embedded Multipliers (37 pages)
- MAX 10 Clocking and PLL (86 pages)
- MAX 10 FPGA (26 pages)
- MAX 10 FPGA (56 pages)
- USB-Blaster II (22 pages)
- GPIO (22 pages)
- LVDS SERDES (27 pages)
- User Flash Memory (33 pages)
- ALTDQ_DQS2 (100 pages)
- Avalon Tri-State Conduit Components (18 pages)
- Cyclone V Avalon-MM (166 pages)
- Cyclone III FPGA Starter Kit (36 pages)
- Cyclone V Avalon-ST (248 pages)
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- Stratix V Avalon-ST (293 pages)
- DDR3 SDRAM High-Performance Controller and ALTMEMPHY IP (10 pages)
- Arria 10 Avalon-ST (275 pages)
- Avalon Verification IP Suite (224 pages)
- Avalon Verification IP Suite (178 pages)
- FFT MegaCore Function (50 pages)
- DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP (140 pages)
- Floating-Point (157 pages)
- Integer Arithmetic IP (157 pages)
- Embedded Peripherals IP (336 pages)
- JESD204B IP (158 pages)
- Low Latency Ethernet 10G MAC (109 pages)
- LVDS SERDES Transmitter / Receiver (72 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (3 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (80 pages)
- IP Compiler for PCI Express (372 pages)
- Parallel Flash Loader IP (57 pages)
- Nios II C2H Compiler (138 pages)
- RAM-Based Shift Register (26 pages)
- RAM Initializer (36 pages)
- Phase-Locked Loop Reconfiguration IP Core (51 pages)
- DCFIFO (28 pages)