Altera Serial Digital Interface (SDI) MegaCore Function - Manual (Page 49)

Chapter 3: Functional Description 3–19
Block Description
February 2013 Altera Corporation Serial Digital Interface (SDI) MegaCore Function
User Guide
Cyclone IV GX devices—EP4CGX30 (F484), EP4CGX50, EP4CGX75, EP4CGX110, and
EP4CGX150—have eight regular transceiver channels from the upper and lower
quads. There are four MPLLs and two GPLLs that you can use to clock the transceiver
channels. Each receiver in EP4CGX50 and EP4CGX75 devices has a clock divider,
which allows one MPLL to drive all the receiver channels. The receiver in EP4CGX110
and EP4CGX150 devices does not have a clock divider, which limits each MPLL to
drive only one receiver channel to accommodate the different standards within a
single quad.
You must supply two receive reference clocks (for example, 148.5 MHz and
148.35 MHz) to the SDI receiver. Implement the PPM detection function in the user
logic to detect the ppm difference between the receive reference clock and the
recovered clock. Based on the difference detected, you must switch between the two
receive reference clocks by toggling the rx_serial_refclk_clkswitch signal,
(
Table 3–16 on page 3–41 ).
f
For more information about the Cyclone IV GX transceiver architecture, refer to
Cyclone IV Transceivers Architecture chapter in volume 2 of the Cyclone IV Device
Handbook.
Cyclone V devices have up to 12 transceiver channels. The SDI support for Cyclone V
transceivers requires the use of the Cyclone V Transceiver Native PHY IP Core. The
native PHY is a thin IP layer with an embedded transceiver PLL.
The Cyclone V Transceiver Native PHY IP Core provides direct access to all control
and status signals of the transceiver channels. Unlike other PHY IP cores, the Native
PHY IP Core does not include an Avalon Memory-Mapped (Avalon-MM) interface.
Instead, it exposes all signals directly as ports. The Cyclone V Transceiver Native PHY
IP Core includes the Standard PCS. You can select the PCS functions and control and
status port that your transceiver PHY requires. The Native Transceiver PHY does not
include an embedded reset controller.
f
For more information about the Cyclone V Transceiver Native PHY IP Core, refer to
the
Altera Transceiver PHY IP Core User Guide .
Transmitter Clocks
The transmitter requires two clocks: a parallel video clock (tx_pclk) and a transmitter
reference clock (tx_serial_refclk).
The parallel video clock samples and processes the parallel video input. For SD-SDI, it
is 27 MHz; for HD-SDI, it is 74.25 or 74.175 MHz; for 3G-SDI, it is 148.5 or 148.35 MHz.
The transceiver uses the transmitter reference clock to generate the high-speed serial
output. The transceiver is configured for 20-bit operation, so the reference clock is
1/20
th of the serial data rate.
1 For SD-SDI, because of the oversampling implementation, the serial data rate is five
times the SDI bit rate (for example, 1,350 Mbps); for the triple-standard SDI,
the oversampling rate is 11.
For SD-SDI operation, the transmitter reference clock can be derived from pclk by
using one of the transceiver PLLs. The PLL can multiply the 27-MHz pclk signal by
5/2.