Altera Serial Digital Interface (SDI) MegaCore Function User Manual
Page 124
A–2
Appendix A: Constraints
Specifying TimeQuest Timing Analyzer Constraints
Serial Digital Interface (SDI) MegaCore Function
February 2013
Altera Corporation
User Guide
shows the flow of the constraint design.
Figure A–1. Constraints Design Flow
Notes to
(1) Applicable for SD-SDI only.
(2) Applicable for Soft SERDES only.
Step 2: Set Timing Exceptions
Step 1: Specify Clock Characteristics
Step 3: Minimize Timing Skew (2)
Set Multicyle Paths (1)
Define Setup and Hold (2)
Specify Asynchronous Clocks
- set_clock_group
(SD, HD, Dual link, 3G, DR, TR,)
- set_false_path
(SD, HD, Dual link, 3G, DR, TR,
Soft Transceiver)
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