Altera Serial Digital Interface (SDI) MegaCore Function - Manual (Page 20)

2–6 Chapter 2: Getting Started
SDI Walkthrough
Serial Digital Interface (SDI) MegaCore Function February 2013 Altera Corporation
User Guide
Setting Up Simulation
An IP functional simulation model is a cycle-accurate VHDL or Verilog HDL model
produced by the Quartus II software. The model allows for fast functional simulation
of IP using industry-standard VHDL and Verilog HDL simulators.
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You may only use these models for simulation and expressly not for synthesis or any
other purposes. Using these models for synthesis creates a nonfunctional design.
To generate an IP functional simulation model for your MegaCore function, follow
these steps:
1. Turn on Generate simulation model.
2. Some third-party synthesis tools can use a netlist that contains only the structure
of the MegaCore function, but not detailed logic, to optimize performance of the
design that contains the MegaCore function. If your synthesis tool supports this
feature, turn on Generate netlist.
3. Click Next (or the Summary tab) to display the Summary page.
Generating Files
You can use the check boxes on the Summary page to enable or disable the generation
of specified files. A gray checkmark indicates a file that is automatically generated; a
red checkmark indicates an optional file.
You can click Back to display the previous page, or click Parameters Settings, EDA,
or Summary, to change any of the MegaWizard options.
To generate the files, follow these steps:
1. Turn on the files you wish to generate.
1
At this stage, you can still click Back to display any of the other pages in the
MegaWizard Plug-In Manager to change any of the parameters.
2. To generate the specified files and close the MegaWizard Plug-In Manager, click
Finish .
1 The generation phase may take several minutes to complete.
1 The Quartus II IP File (.qip) is a file generated by the parameter editor, and
contains information about the generated IP core. You are prompted to add
this .qip file to the current Quartus II project at the time of file generation.
In most cases, the .qip file contains all of the necessary assignments and
information required to process the core or system in the Quartus II
compiler. Generally, a single .qip file is generated for each MegaCore
function or system in the Quartus II compiler.
3. Click Exit to close the Generation window.