Altera Serial Digital Interface (SDI) MegaCore Function User Manual
Page 48
3–18
Chapter 3: Functional Description
Block Description
Serial Digital Interface (SDI) MegaCore Function
February 2013
Altera Corporation
User Guide
Transceiver Controller
To achieve the desired receiver functionality for the SDI, the transceiver controller
controls the transceiver.
When the interface receives SD-SDI, the transceiver receiver PLL locks to the receiver
reference clock.
When the interface receives HD-SDI, the transceiver receiver PLL is first trained by
locking to the receiver reference clock. When the PLL is locked, it can then track the
actual receiver data rate. If a period of time passes without a valid SDI signal, the PLL
is retrained with the reference clock and the process is repeated.
The transceiver controller allows the transceiver to support the reception of both
SD-SDI and HD-SDI data by using an algorithm that alternately searches for one rate
then the other. First, it looks for an HD-SDI signal, training the PLL then letting it
track the serial data rate. If a valid HD-SDI signal is not seen within 0.1 s, the receiver
path is reset and the PLL is trained for SD-SDI. Conversely, if a valid SD-SDI signal is
not seen within 0.1 s, the receiver path is reset and the process repeated. The
transceiver controller also resets and starts searching again if the SDI receiver
indicates that the signal is no longer valid.
For HD-SDI operation, if 100 consecutive bits with the same value are seen, the
receiver is reset and the PLL is retrained. The maximum legal run length for HD-SDI
is 59 bits.
f
For more information on the Stratix GX transceiver, refer to the
Transceiver—Arria GX, Arria II GX, Arria V, Cyclone IV GX, Cyclone V,
Stratix II GX, Stratix IV GX, and Stratix V Devices
The Arria GX, Arria II GX, Arria V, Cyclone IV GX, Stratix II GX, Stratix IV GX, or
Stratix V transceiver deserializes the high-speed serial input. For HD-SDI, the CDR
function performs the deserialization and locks the receiver PLL to the receiver data.
For SD-SDI, the transceiver provides a fixed frequency oversample of the serial data
with the receiver PLL constantly locked to a reference clock, which allows the
transceiver to support the 270-Mbps data rate.
The transceiver can process either SD-SDI or HD-SDI data. The data rate can be
automatically detected so that the interface can handle both SD-SDI and HD-SDI
without the need for device reconfiguration.
Arria GX, Arria II GX, Arria V, Stratix II GX, Stratix IV GX, and Stratix V devices have
two transmitter PLLs per quad. Each quad allows two independent transmitter rates.
Receivers in a quad share a common training clock, but have independent receiver
PLLs. Because the same training clock is used for SD-SDI and HD-SDI, receivers can
accommodate the different standards within a single quad.
Arria II GX (including Arria II GZ) and Stratix IV GX devices also provide the option
for you to enable an additional serial reference clock port. This additional clock port
allows you to have two different clock rates for different data rates using a single
transceiver block, with the ability to switch between the desired clock rates (for
example, 148.5 MHz and 148.35 MHz).