Altera Serial Digital Interface (SDI) MegaCore Function - Manual (Page 123)

February 2013 Altera Corporation Serial Digital Interface (SDI) MegaCore Function
User Guide
A. Constraints
For the SDI MegaCore function to work reliably, you must implement the following
Quartus II constraints:
■ Specify clock characteristics
■ Set timing exceptions such as false path, maximum and minimum delays, and
multicycle path
■ Minimize the timing skew among the paths from I/O pins to the four sampling
registers
■ Set the oversampling clock that the oversampling interface to 135 MHz uses as an
independent clock domain
Specifying TimeQuest Timing Analyzer Constraints
To ensure your design meets timing and other requirements, you must constrain the
design. This section provides the necessary steps to properly constrain your SDI
design using the TimeQuest timing analyzer.
1. Make sure that TimeQuest is specified as the default timing analyzer in the Timing
Analysis Settings page of the Settings dialog box.
2. Perform initial compilation to create an initial design database before you specify
timing constraints for your design. On the Processing menu, click Start
Compilation
. A message indicates when compilation is complete.
3. On the Tools menu, click TimeQuest Timing Analyzer.
4. Create timing netlist, double-click Create Timing Netlist in the Tasks pane. The
timing netlist appears in the Report pane.
5. Specify timing constraints and exceptions. To enter your timing requirements, you
can use constraint entry dialog boxes or edit the previously created .sdc file.
6. To save your constraints in an .sdc file, on the Constraints menu, click Write SDC
File .