Cyclone devices only, Classic timing analyzer, Timequest timing analyzer – Altera Serial Digital Interface (SDI) MegaCore Function User Manual

Page 131

Appendix A: Constraints

A–9

Constraints for the SDI Soft Transceiver

February 2013

Altera Corporation

Serial Digital Interface (SDI) MegaCore Function

User Guide

Cyclone Devices Only

These constraints apply to Cyclone devices only (not Cyclone II, Cyclone III, or other
device families).

Classic Timing Analyzer

Use the following constraints for the Classic timing analyzer:

set_global_assignment -name FMAX_REQUIREMENT "27 MHz" -section_id
input_refclk

set_instance_assignment -name CLOCK_SETTINGS input_refclk -to
rx_27_refclk

set_instance_assignment -name CLOCK_SETTINGS rxclk -to
"|sdi_megacore_top:sdi_megacore_top_inst|sdi_clocks:u_s
di_clocks|clkdiv_2p5:cyc_rx_pll_gen.u_clkdiv|clkdiv"

set_global_assignment -name BASED_ON_CLOCK_SETTINGS input_refclk -
section_id rxclk

set_global_assignment -name MULTIPLY_BASE_CLOCK_PERIOD_BY 5 -section_id
rxclk

set_global_assignment -name DIVIDE_BASE_CLOCK_PERIOD_BY 25 -section_id
rxclk

set_global_assignment -name ENABLE_CLOCK_LATENCY ON

TimeQuest Timing Analyzer

Use the following constraints for the TimeQuest timing analyzer:

derive_pll_clocks -use_tan_name

create_clock -name rx_27_refclk -period 37.037 -waveform { 0.000 18.518
} [get_ports {rx_27_refclk}]

create_clock -name tx_27_refclk -period 37.037 -waveform { 0.000 18.518
} [get_ports {tx_27_refclk}]