Receiver, Receiver clocks, Transceiver—stratix gx devices – Altera Serial Digital Interface (SDI) MegaCore Function User Manual
Page 43: Transmitter clocks, Receiver –13, Receiver clocks –13, Transceiver—stratix gx devices –13, Transmitter clocks –13
Chapter 3: Functional Description
3–13
Block Description
February 2013
Altera Corporation
Serial Digital Interface (SDI) MegaCore Function
User Guide
Receiver
For the receiver, in the soft-logic transceiver the serial data stream from the LVDS
input buffer is sampled using four different clocks phase-shifted by 90
° from each
other. Two out of these four clocks are created from an on-chip PLL. The two
remaining clocks are created by inversion of the PLL clock outputs.
Samples are then all converted to the same clock domain and deserialized into a 10-bit
parallel word. The serial clock that samples the bit stream must be 337.5 MHz, which
is 5/4 of the incoming bit (270-bit rate × 5/4 × 4 sample per clock = 1,350 Mbps)
The parallel clock that extracts data from the deserializer is running at 135 MHz.
To achieve timing, you must correctly constrain your design, refer to
.
Receiver Clocks
The deserializer requires three clocks (refer to
), which you
can generate from an external source.
Transceiver—Stratix GX Devices
The Stratix GX transceiver deserializes the high-speed serial input. For HD-SDI, the
clock data recovery (CDR) function performs the deserialization and locks the
receiver PLL to the receiver data. For SD-SDI, the transceiver provides a fixed
frequency oversample of the serial data with the receiver PLL constantly locked to a
reference clock, which allows the transceiver to support the 270-Mbps data rate.
The transceiver can process either SD-SDI or HD-SDI data. The data rate can be
automatically detected so that the interface can handle both SD-SDI and HD-SDI
without the need for device reconfiguration.
In Stratix GX devices, the transmitters in a quad share a common reference clock,
which prevents them from operating independently.
Receivers in a quad share a common training clock, but have independent receiver
PLLs. Because the same training clock is used for SD-SDI and HD-SDI, receivers can
accommodate the different standards within a single quad.
Transmitter Clocks
The transmitter requires two clocks: a parallel video clock (tx_pclk) and a transmitter
reference clock (tx_serial_refclk).
The parallel video clock samples and processes the parallel video input. For SD-SDI, it
is 27 MHz; for HD-SDI, it is 74.25 or 74.175 MHz.
The transceiver uses the transmitter reference clock to generate the high-speed serial
output. The transceiver is configured for 20-bit operation, so the reference clock is
1/20
th
of the serial data rate.
1
For SD-SDI, because of the oversampling implementation, the serial data rate is five
times the SDI bit rate (for example, 1,350 Mbps).
For HD-SDI operation, pclk can drive the transmitter reference clock.