Altera Serial Digital Interface (SDI) MegaCore Function - Manual (Page 137)

February 2013 Altera Corporation Serial Digital Interface (SDI) MegaCore Function
User Guide
Additional Information
This chapter provides additional information about the document and Altera.
Document Revision History
The following table shows the revision history for this user guide.
Date Version Changes
February 2013 12.1
■ Updated Table 1–2 , Table 1–4 , Table 1–5 , and Table 1–7 for version 12.1 release.
■ Updated information on duplex setting in Table 3–10 .
■ Updated information on rx_video_format signal in Table 3–12 .
■ Added a note in Table 3–13 to include information about Arria V and Stratix V devices.
■ Added Table 3–14 —transceiver PHY management clock and reset signals.
■ Updated information on rx_status signal in Table 3–18 .
■ Added data width information for SDI_RECONFIG_TOGXB and SDI_RECONFIG_FROMGXB
signals in
Table 3–19 .
■ Updated the Starting channel number parameter description in Table 3–21 .
■ Added reset sequence information and timing diagram in Figure 3–25 .
November 2011 11.1
■ Added information about Arria V and Stratix V devices.
■ Updated Table 1–2 , Table 1–5 , Table 1–6 , and Table 1–7 for version 11.1 release.
■ Updated “Parameterizing” section to include additional steps to turn on the Enable TX PLL
select for 1/1.000 and 1/1.001 data rate reconfiguration option.
■ Updated “Transmitter Clocks” , “Transceiver—Arria GX, Arria II GX, Arria V, Cyclone IV GX,
Cyclone V, Stratix II GX, Stratix IV GX, and Stratix V Devices” , Table 3–7 , Table 3–9 ,
Figure 3–3 , Figure 3–8 , to include information about the optional serial reference clock
feature.
■ Updated Table 3–21 with Enable TX PLL select for 1/1.000 and 1/1.001 data rate
reconfiguration parameter.
■ Updated information in the “Transceiver Dynamic Reconfiguration for Dual Standard and
Triple Standard Receivers” .
■ Updated Table 4–1 , Table 4–4 , and Table 4–14 to include information about asynchronous
and synchcronous modes.
July 2011 11.0
■ Added information about accessing transceiver.
■ Updated Table 3–12 with new signals, refclk_rate and rx_video_format.
■ Updated the high-level block diagram of design example for the SDI Audio IP Core to
include AES input and output modules.
■ Updated the SDI Audio IP Core register maps.
December 2010 10.1
■ Added two new GUI parameters for SDI MegaCore function: Enable Spread Spectrum
feature and Tolerance to consecutive missed EAV.
■ Added a chapter on the SDI Audio IP Cores: SDI Audio Embed, Audio Extract, Clocked
Audio Input, and Clocked Audio Output MegaCore functions.