Altera Serial Digital Interface (SDI) MegaCore Function - Manual (Page 71)

Chapter 3: Functional Description 3–41
Signals
February 2013 Altera Corporation Serial Digital Interface (SDI) MegaCore Function
User Guide
Table 3–14 lists the transceiver PHY management clock and reset signals.
Table 3–15 lists the soft transceiver clock signals.
Table 3–16 lists the interface signals.
Table 3–14. Transceiver PHY Management Signals (1)
Signal Direction Description
phy_mgmt_clk Input
Avalon-MM clock input for the transceiver PHY management
interface. Use the same clock for the PHY management interface and
transceiver reconfiguration. The frequency range is 100-125 MHz to
meet the specification of the transceiver reconfiguration clock.
phy_mgmt_clk_reset Input
Reset signal for the transceiver PHY management interface. This
signal is active high and level sensitive. This signal can be tied to the
same reset port as tx_rst or rx_rst signal in simplex mode.
In duplex mode, this reset signal acts as a global reset for both the
transmitter and receiver. If you require a different reset for the
transmitter and receiver, separate this signal from the tx_rst and
rx_rst
signal.
Note to Table 3–14 :
(1) The transceiver PHY management clock and reset signals are available for Stratix V and Arria V devices only.
Table 3–15. Soft Transceiver Clock Signals
Signal Direction Description
rx_sd_refclk_337 Input Soft transceiver 337.5-MHz sampling clock.
rx_sd_refclk_337_90deg Input Soft transceiver 337.5-MHz sampling clock with 90 ° phase shift.
rx_sd_refclk_135 Input Soft transceiver 135-MHz parallel clock for receiver.
tx_sd_refclk_270 Input Soft transceiver 270-MHz parallel clock for transmitter.
Table 3–16. Interface Signals (Part 1 of 5)
Signal Width Direction Description
enable_crc [(N – 1):0] Input Enables CRC insertion for HD-SDI and 3G-SDI.
enable_hd_search 1 Input
Enables search for HD-SDI signal in dual or triple standard
mode.
enable_sd_search 1 Input
Enables search for SD-SDI signal in dual or triple standard
mode.
enable_3g_search 1 Input Enables search for 3G-SDI signal in triple standard mode.
enable_ln [(N – 1):0] Input
Enables line number insertion for HD-SDI and 3G-SDI
modes.
en_sync_switch 1 Input
Enables aligner and format blocks to realign immediately
so that the downstream is completely non-disruptive.
rst_rx 1 Input
Reset signal, which holds the receiver in reset. It must be
synchronous to rx_serial_refclk clock domain for the
receiver. Issues a reset to the SDI MegaCore function after
power-up to ensure reliable operation. Refer to
Figure 3–29 .
For HD-SDI dual link receiver, assert this signal when both
link A and link B are ready for the first time.