Altera Serial Digital Interface (SDI) MegaCore Function - Manual (Page 126)

A–4 Appendix A: Constraints
Specifying TimeQuest Timing Analyzer Constraints
Serial Digital Interface (SDI) MegaCore Function February 2013 Altera Corporation
User Guide
The following constraints are specifically used to constrain a duplex SDI MegaCore
function targeting Stratix IV device:
■ Specify Clock Characteristics
■ Set Multicycle Paths
■ Minimize Timing Skew
Specify Clock Characteristics
Use the following constraints for the TimeQuest timing analyzer:
■ SD-SDI (rx_sd_oversample_clk_in = 67.5 MHz, tx_pclk = 27 MHz,
tx_serial_refclk
= 67.5 MHz)
create_clock -name {rx_sd_oversample_clk_in} -period 14.814 -waveform { 0.000 7.407
} [get_ports {rx_sd_oversample_clk_in}]
create_clock -name {tx_pclk} -period 14.814 -waveform { 0.000 7.407 } [get_ports
{tx_pclk}]
create_clock -name {tx_serial_refclk} -period 14.814 -waveform { 0.000 7.407 }
[get_ports {tx_serial_refclk}]
■ HD-SDI, HD-SDI dual link (rx_serial_refclk = 74.25 MHz, tx_pclk =
74.25 MHz, tx_serial_refclk = 74.25 MHz)
create_clock -name {rx_serial_refclk} -period 13.468 -waveform { 0.000
6.734 } [get_ports {rx_serial_refclk}]
create_clock -name {tx_pclk} -period 13.468 -waveform { 0.000 6.734 }
[get_ports {tx_pclk}]
Soft transceiver
SDI
— —
switchline,
get_clocks
receive_pcs0|clkout
(gxb_rxclk)
Setup—1.5 clocks
(4.43 ns) from the
337.5-MHz zero-degree
clock to the 135-MHz
clock
Hold—zero clocks from
the 337.5-MHz clock to
the 135-MHz clock
Note to Table A–2 :
(1) Switchline is an internal signal equivalent to the en_switch_reg signal in Figure 3–6 .
Table A–2. Step 2: Set Timing Exceptions (Part 2 of 2)
Standard
Set Multicycle
Paths
set_clock_group set_false_path (1)
Define Setup and Hold
Relationship
Table A–3. Step 3: Minimize the Timing Skew
Standard Minimize Timing Skew
SD-SDI —
HD-SDI, HD-SDI dual link —
3G-SDI —
DR, TR —
Soft transceiver SDI I/O to sample_a|b|c|d[0] path as short as possible