Transmitter transceiver interface, Transmitter transceiver interface –16, Transmitter retiming – Altera Serial Digital Interface (SDI) MegaCore Function User Manual
Page 46: Hd-sdi two-times oversampling
3–16
Chapter 3: Functional Description
Block Description
Serial Digital Interface (SDI) MegaCore Function
February 2013
Altera Corporation
User Guide
shows the receiver clocks for different video standards.
Transmitter Transceiver Interface
Altera provides a transceiver interface, which interfaces the transceiver to the SDI
function. The transceiver interface implements the following functions:
■
■
■
SD-SDI Transmitter Oversampling
1
When using the two-times oversampling transmitters in Stratix GX devices, you
cannot have HD-SDI receivers in the same quad. The quad requires the same
frequency reference clocks for both the receivers and transmitters within a quad.
HD-SDI receivers and two-times oversampling transmitters have different frequency
reference clocks (refer to
and
).
Transmitter Retiming
The txdata parallel data input to the transceiver must be synchronous and phase
aligned to the tx_coreclk transceiver clock input. SD-SDI (and optionally HD-SDI)
requires a retiming function, because of the oversampling logic. The transmitter uses a
small 16 × 20 FIFO buffer for the retiming.
Figure 3–9. Receiver Clocks
rx_clk
rx_data
rx_data_valid_out
V
V
V
V
SDI MegaCore
Function
74.25/74.175 MHz
Serial Data
HD-SDI
rx_clk = 74.25 MHz
rx_data_valid_out
rx_clk
rx_data
rx_data_valid_out
V
V
V
V
SDI MegaCore
Function
67.5 MHz
Serial Data
SD-SDI
rx_clk = 67.5 MHz
rx_data_valid_out
SDI MegaCore
Function
67.5 MHz
Serial Data
Dual Standard
rx_clk = 67.5 or 74 MHz
rx_data_valid_out