Altera Serial Digital Interface (SDI) MegaCore Function - Manual (Page 127)

Appendix A: Constraints A–5
Specifying TimeQuest Timing Analyzer Constraints
February 2013 Altera Corporation Serial Digital Interface (SDI) MegaCore Function
User Guide
create_clock -name {tx_serial_refclk} -period 13.468 -waveform { 0.000
6.734 } [get_ports {tx_serial_refclk}]
■ 3G-SDI (rx_serial_refclk = 148.5 MHz, tx_pclk = 148.5 MHz, tx_serial_refclk
= 148.5 MHz)
create_clock -name {rx_serial_refclk} -period 6.734 -waveform { 0.000
3.367 } [get_ports {rx_serial_refclk}]
create_clock -name {tx_pclk} -period 6.734 -waveform { 0.000 3.367 }
[get_ports {tx_pclk}]
create_clock -name {tx_serial_refclk} -period 6.734 -waveform { 0.000
3.367 } [get_ports {tx_serial_refclk}]
■ Dual standard, triple standard SDI
create_clock -name {rx_serial_refclk} -period 6.734 -waveform { 0.000
3.367 } [get_ports {rx_serial_refclk}]
create_clock -name {tx_serial_refclk} -period 6.734 -waveform { 0.000
3.367 } [get_ports {tx_serial_refclk}]
create_clock -name {tx_pclk} -period 6.734 -waveform { 0.000 3.367 }
[get_ports {tx_pclk}]
■ Soft transceiver SDI
create_clock -name {rx_sd_refclk_135} -period 7.407 -waveform { 0.000
3.703 } [get_ports {rx_sd_refclk_135}]
create_clock -name {rx_sd_refclk_337} -period 2.967 -waveform { 0.000
1.484 } [get_ports {rx_sd_refclk_337}]
create_clock -name {rx_sd_refclk_337_90deg} -period 2.967 -waveform {
0.000 1.484 } [get_ports {rx_sd_refclk_337_90deg}]
create_clock -name {tx_sd_refclk_270} -period 3.703 -waveform { 0.000
1.852 } [get_ports {tx_sd_refclk_270}]
create_clock -name {tx_pclk} -period 37.037 -waveform { 0.000 18.519 }
[get_ports {tx_pclk}]
Set Multicycle Paths
In some device families and speed grades, timing violations may occur in the format
block of the SDI MegaCore function. For SD-SDI, these violations are multicycle, and
can be fixed by applying the following constraints to your design, (these constraints
apply only to SD-SDIs; they are single-cycle paths in all other video standards).
set_multicycle_path -setup -end -from [get_keepers
{sdi_megacore_top:sdi_megacore_top_inst|sdi_txrx_port:sdi_txrx_port_ge
n[0].u_txrx_port|sdi_format:format_gen.u_format|*}] -to [get_keepers
{sdi_megacore_top:sdi_megacore_top_inst|sdi_txrx_port:sdi_txrx_port_ge
n[0].u_txrx_port|sdi_format:format_gen.u_format|*}] 2
set_multicycle_path -hold -end -from [get_keepers
{sdi_megacore_top:sdi_megacore_top_inst|sdi_txrx_port:sdi_txrx_port_ge
n[0].u_txrx_port|sdi_format:format_gen.u_format|*}] -to [get_keepers
{sdi_megacore_top:sdi_megacore_top_inst|sdi_txrx_port:sdi_txrx_port_ge
n[0].u_txrx_port|sdi_format:format_gen.u_format|*}] 1
Specify Clocks that are Exclusive or Asynchronous
The SDI MegaCore function may show timing violations in slower speed grade
devices. These paths are not required to have fast timing, so you can use the following
constraints to remove these timing paths. You can use the command
set_clock_groups
or set_false_path.