Non cyclone devices, Classic timing analyzer, Timequest timing analyzer – Altera Serial Digital Interface (SDI) MegaCore Function User Manual

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Appendix A: Constraints

Constraints for the SDI Soft Transceiver

Serial Digital Interface (SDI) MegaCore Function

February 2013

Altera Corporation

User Guide

Non Cyclone Devices

These constraints apply to all device families (excluding Cyclone, but including
Cyclone II , Cyclone III and Cyclone IV devices) that are configured to use a soft
transceiver for their receivers.

Define the following setup and hold relationship between the 135-MHz clocks and the
337.5-MHz zero-degree clocks:

■

Setup—1.5 clocks (4.43 ns) from the 337.5-MHz zero-degree clock to the 135-MHz
clock

■

Hold—zero clocks from the 337.5-MHz clock to the 135-MHz clock

If you choose to include the PLLs inside the MegaCore function, modify the following
constraints and apply them to your design. Alternatively, apply similar constraints to
the clocks connected to the rx_sd_refclk_337 and rx_sd_refclk_135 signals on your
SDI MegaCore function.

Classic Timing Analyzer

Use the following constraints for the Classic timing analyzer:

TimeQuest Timing Analyzer

Use the following constraints for the TimeQuest timing analyzer:

set_max_delay 4.43 -from
{|sdi_megacore_top:sdi_megacore_top_
inst|sdi_clocks:u_sdi_clocks|stratix_c2_pll_sclk:u_rx_pll|altpll:altpl
l_component|_clk0} -to
{|sdi_megacore_top:sdi_megacore_top_
inst|sdi_clocks:u_sdi_clocks|stratix_c2_pll_sclk:u_rx_pll|altpll:altpl
l_component|_clk2}

set_min_delay 0 -from {
|sdi_megacore_top:sdi_megacore_top_i
nst|sdi_clocks:u_sdi_clocks|stratix_c2_pll_sclk:u_rx_pll|altpll:altpll
_component|_clk0} -to
{|sdi_megacore_top:sdi_megacore_top_
inst|sdi_clocks:u_sdi_clocks|stratix_c2_pll_sclk:u_rx_pll|altpll:altpl
l_component|_clk2}