Altera Serial Digital Interface (SDI) MegaCore Function - Manual (Page 128)

A–6 Appendix A: Constraints
Specifying TimeQuest Timing Analyzer Constraints
Serial Digital Interface (SDI) MegaCore Function February 2013 Altera Corporation
User Guide
1 The following SDC commands are only applicable for duplex core and Stratix IV
devices, you must use the constraint entry dialog boxes to constrain the separate
receiver or transmitter core and other device families.
■ SD-SDI
set_clock_groups -exclusive -group [get_clocks {tx_pclk}] -group
[get_clocks
{sdi_megacore_top_inst|sdi_txrx_port_gen[0].u_txrx_port|gen_duplex_alt
4gxb.u_gxb|alt4gxb_component|auto_generated|transmit_pcs0|clkout}]
set_false_path -from [get_keepers
{sdi_megacore_top:sdi_megacore_top_inst|sdi_txrx_port:sdi_txrx_port_ge
n[0].u_txrx_port|switchline}] -to [get_clocks
{sdi_megacore_top_inst|sdi_txrx_port_gen[0].u_txrx_port|gen_duplex_alt
4gxb.u_gxb|alt4gxb_component|auto_generated|receive_pcs0|clkout}]
■ HD-SDI, 3G-SDI, dual standard, triple standard SDI
set_clock_groups -exclusive -group [get_clocks {rx_serial_refclk}] -
group [get_clocks
{sdi_megacore_top_inst|sdi_txrx_port_gen[0].u_txrx_port|gen_duplex_alt
4gxb.u_gxb|alt4gxb_component|auto_generated|receive_pcs0|clkout}]
set_clock_groups -exclusive -group [get_clocks {tx_pclk}] -group
[get_clocks
{sdi_megacore_top_inst|sdi_txrx_port_gen[0].u_txrx_port|gen_duplex_alt
4gxb.u_gxb|alt4gxb_component|auto_generated|transmit_pcs0|clkout}]
set_false_path -from [get_keepers
{sdi_megacore_top:sdi_megacore_top_inst|sdi_txrx_port:sdi_txrx_port_ge
n[0].u_txrx_port|switchline}] -to [get_clocks
{sdi_megacore_top_inst|sdi_txrx_port_gen[0].u_txrx_port|gen_duplex_alt
4gxb.u_gxb|alt4gxb_component|auto_generated|receive_pcs0|clkout}]
■ HD-SDI dual link (for the additional channel)
set_clock_groups -exclusive -group [get_clocks {rx_serial_refclk}] -
group [get_clocks
{sdi_megacore_top_inst|sdi_txrx_port_gen[1].u_txrx_port|gen_duplex_alt
4gxb.u_gxb|alt4gxb_component|auto_generated|receive_pcs0|clkout}]
set_false_path -from [get_keepers
{sdi_megacore_top:sdi_megacore_top_inst|sdi_txrx_port:sdi_txrx_port_ge
n[0].u_txrx_port|switchline}] -to [get_clocks
{sdi_megacore_top_inst|sdi_txrx_port_gen[0].u_txrx_port|gen_duplex_alt
4gxb.u_gxb|alt4gxb_component|auto_generated|receive_pcs0|clkout}]
set_clock_groups -exclusive -group [get_clocks {tx_pclk}] -group
[get_clocks
{sdi_megacore_top_inst|sdi_txrx_port_gen[1].u_txrx_port|gen_duplex_alt
4gxb.u_gxb|alt4gxb_component|auto_generated|transmit_pcs0|clkout}]
set_false_path -from [get_keepers
{sdi_megacore_top:sdi_megacore_top_inst|sdi_txrx_port:sdi_txrx_port_ge
n[1].u_txrx_port|switchline}] -to [get_clocks
{sdi_megacore_top_inst|sdi_txrx_port_gen[1].u_txrx_port|gen_duplex_alt
4gxb.u_gxb|alt4gxb_component|auto_generated|receive_pcs0|clkout}]
Define the Setup and Hold Relationship between 135-MHz Clocks and
337.5-MHz Zero-degree Clocks
These constraints apply only to soft transceiver SDI.
■ Setup—1.5 clocks (4.43 ns) from the 337.5-MHz zero-degree clock to the 135-MHz
clock