Altera Serial Digital Interface (SDI) MegaCore Function - Manual (Page 133)

February 2013 Altera Corporation Serial Digital Interface (SDI) MegaCore Function
User Guide
B. Clocking
Figure B–1 shows the transceiver clocks for the SDI MegaCore function for version 7.0
and previous.
Figure B–2 shows how you must clock the transceivers for current SDI cores. You can
now derive all clocks from a single 148.5-MHz voltage controlled crystal oscillator
(VCXO) and the transceivers require no external multiplexing.
Figure B–3 shows how you must clock the transceivers for version 7.1 and later SDI
cores with international clocking. Both American and European standards are catered
for.
Figure B–1. Version 7.0 and Earlier Clocks
SDI Out
SDI Receiver
Transceiver
74-MHz
VCXO
Phase
Frequency
Detector
SDI Transmitter
Transceiver 67.5-MHz
VCXO
/2
HD SD
PLL
11/5
Figure B–2. Version 7.1 and Later Clocks
SDI Out
SDI Receiver
Transceiver
148.5-MHz
VCXO
Phase
Frequency
Detector
SDI Transmitter
Transceiver
/2
HD SD/3G
Figure B–3. Version 7.1 and Later International Clocks
SDI Out
SDI Receiver
Transceiver
148.5-MHz
VCXO
Phase
Frequency
Detector
SDI Transmitter
Transceiver 148.35-MHz
VCXO
/2
HD SD