Altera Serial Digital Interface (SDI) MegaCore Function - Manual (Page 112)

4–24 Chapter 4: SDI Audio IP Cores
Simulating the Testbench
Serial Digital Interface (SDI) MegaCore Function February 2013 Altera Corporation
User Guide
As the SDI Audio Embed and Audio Extract MegaCore functions use an Avalon-MM
slave interface to access the control registers, the most convenient way for you to
instantiate the components are within SOPC Builder. You are provided with the
component declaration TCL files to support either the ordinary AES audio inputs or
the Avalon-ST audio interface.
If you select a MegaCore function with ordinary audio interfaces within SOPC
Builder, the audio interfaces are exposed for connection at the top level of the SOPC
Builder design. Otherwise, the Avalon-ST audio interfaces are exposed within SOPC
Builder for connection to other components.
Alternatively, you can also instantiate the SDI Audio Embed and Audio Extract
MegaCore functions directly in your RTL and drive the direct control interface signals
directly without the accompanying Avalon-MM register interface.
Simulating the Testbench
Altera provides a fixed testbench as an example to simulate the SDI Audio cores. You
can obtain the testbench from ip/altera/audio_embed/simulation directory. To use the
testbench with the ModelSim simulator, follow these steps:
1. Open the Quartus II software.
2. On the File menu, click the New Project Wizard.
3. Specify the working directory to
ip/altera/audio_embed/simulation/megacore_build , and give a sensible name for
your project and top-level entity.
4. Click Next, and select Stratix IV for the device family.
5. Click Finish.
6. On the Tools menu, click the MegaWizard Plug-In Manager.
7. Select Edit an existing custom megafunction variation and click Next.
8. Locate and click the variant audio_embed_avalon_top.v file and click Next.
9. In the SDI Audio Embed parameter editor, click Finish to regenerate the variant
audio_embed_avalon_top.v file and produce the simulation model.
10. Repeat steps 6 to 9 for the remaining variant files provided in the megacore_build
directory.
11. In a text editor, open the simulation script, simulation/run.tcl. Edit the script to
point to your installation of the Quartus II software. For example:
set quartusdir /tools/acds/11.0/157/linux32/quartus/eda/sim_lib/
12. Start the ModelSim simulator.
13. Run run.tcl in the simulation directory. This file compiles the design. A selection of
signals appears on the waveform viewer. The simulation runs automatically,
providing a pass or fail indication upon completion.
Use this testbench to simulate the SDI Audio Embed MegaCore and the associated
SDI Audio Extract MegaCore functions, and the SDI Clocked Audio Input MegaCore
and the associated Clocked Audio Output MegaCore functions.