Altera Serial Digital Interface (SDI) MegaCore Function - Manual (Page 42)

3–12 Chapter 3: Functional Description
Block Description
Serial Digital Interface (SDI) MegaCore Function February 2013 Altera Corporation
User Guide
Transceiver Clock
Figure 3–7 shows the general clocking scheme for the receiver.
Transceiver—Soft-Logic Implementation
The soft-logic implementation differs for the transmitter and the receiver.
Transmitter
For the transmitter, in the soft-logic transceiver a 10-bit parallel word is converted into
a serial data output format. A 10-bit shift register loaded at the word rate from the
encoder and unloaded at the bit rate of the LVDS output buffer is implemented for
that function. A PLL that multiplies a 27-MHz reference clock by ten provides the
bit-rate clock and enables jitter-controlled SDI transmit serialization.
Transmitter Clocks
The serializer requires a 270-MHz clock, which you can generate from an external
source (tx_sd_refclk_270).
The 27-MHz parallel video clock (tx_pclk) samples and processes the parallel video
input.
Transmitter Clock Multiplexer Option
This is a new feature introduced in version 11.1. The transmitter block has the option
of receiving an additional reference clock to allow dynamic switching between the
1/1000 and 1/1.001 data rates. This feature is available in Arria II, Stratix IV, and
HardCopy IV devices.
By default, you can use the tx_serial_refclk for any normal SDI operations and the
tx_serial_refclk1
as an additional clock input parameter. You can then switch to the
clock source selected by using the transceiver dynamic reconfiguration.
Figure 3–7. Receiver Clocking Scheme
Protocol Block (Receiver) Transceiver Interface Block Transceiver Block
ALTGXB
rxclk
rxword[19:0]
rxdata[19:0]
rx_refclk rx_cruclk
cal_blk_clk
reconfig_clk
gxb_rxword[19:0] rx_dataout[19:0]
gxb_refclk rxclk rx_clkout
rxclk
rx_serial_refclk
gxb2_cal_clk
sdi_reconfig_clk
sdi_rx
(serial data in)